From patchwork Fri Mar 5 14:59:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudio Fontana X-Patchwork-Id: 1447924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DsWQr2BRkz9sW1 for ; Sat, 6 Mar 2021 02:11:16 +1100 (AEDT) Received: from localhost ([::1]:38534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIC6k-0006ng-8z for incoming@patchwork.ozlabs.org; Fri, 05 Mar 2021 10:11:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIBw9-0001wp-P7 for qemu-devel@nongnu.org; Fri, 05 Mar 2021 10:00:26 -0500 Received: from mx2.suse.de ([195.135.220.15]:59726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIBw7-0003wg-3a for qemu-devel@nongnu.org; Fri, 05 Mar 2021 10:00:17 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 92A54AFF1; Fri, 5 Mar 2021 14:59:52 +0000 (UTC) From: Claudio Fontana To: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= Subject: [RFC v4 18/33] target/arm: move sve_zcr_len_for_el to common_cpu Date: Fri, 5 Mar 2021 15:59:26 +0100 Message-Id: <20210305145941.32020-19-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210305145941.32020-1-cfontana@suse.de> References: <20210305145941.32020-1-cfontana@suse.de> MIME-Version: 1.0 Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" it is required by arch-dump.c and cpu.c, so apparently we need this for KVM too Signed-off-by: Claudio Fontana --- target/arm/cpu-common.c | 43 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 33 ------------------------------- 2 files changed, 43 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index 694e5d73f3..540793e4c0 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -231,3 +231,46 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, mask &= ~CACHED_CPSR_BITS; env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); } + +/* + * these are AARCH64-only, but due to the chain of dependencies, + * between HELPER prototypes, hflags, cpreg definitions and functions in + * tcg/ etc, it becomes incredibly messy to add what should be here: + * + * #ifdef TARGET_AARCH64 + */ + +static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +{ + uint32_t end_len; + + end_len = start_len &= 0xf; + if (!test_bit(start_len, cpu->sve_vq_map)) { + end_len = find_last_bit(cpu->sve_vq_map, start_len); + assert(end_len < start_len); + } + return end_len; +} + +/* + * Given that SVE is enabled, return the vector length for EL. + */ +uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +{ + ARMCPU *cpu = env_archcpu(env); + uint32_t zcr_len = cpu->sve_max_vq - 1; + + if (el <= 1) { + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + } + if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + } + + return sve_zcr_get_valid_len(cpu, zcr_len); +} + +/* #endif TARGET_AARCH64 , see matching comment above */ diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 9e6f21620e..430102e1ef 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -390,39 +390,6 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - end_len = start_len &= 0xf; - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len = find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - -/* - * Given that SVE is enabled, return the vector length for EL. - */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) -{ - ARMCPU *cpu = env_archcpu(env); - uint32_t zcr_len = cpu->sve_max_vq - 1; - - if (el <= 1) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); - } - if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); - } - - return sve_zcr_get_valid_len(cpu, zcr_len); -} - void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env = &cpu->env;