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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id z13sm33854690wrh.65.2021.03.03.13.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v4 19/28] target/arm/internals: Fix code style for checkpatch.pl Date: Wed, 3 Mar 2021 22:46:59 +0100 Message-Id: <20210303214708.1727801-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Cornelia Huck , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 05cebc8597c..d6ace004855 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -251,7 +251,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) return pamax_map[parange]; } -/* Return true if extended addresses are enabled. +/* + * Return true if extended addresses are enabled. * This is always the case if our translation regime is 64 bit, * but depends on TTBCR.EAE for 32 bit. */ @@ -262,20 +263,24 @@ static inline bool extended_addresses_enabled(CPUARMState *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); } -/* Update a QEMU watchpoint based on the information the guest has set in the +/* + * Update a QEMU watchpoint based on the information the guest has set in the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ void hw_watchpoint_update(ARMCPU *cpu, int n); -/* Update the QEMU watchpoints for every guest watchpoint. This does a +/* + * Update the QEMU watchpoints for every guest watchpoint. This does a * complete delete-and-reinstate of the QEMU watchpoint list and so is * suitable for use after migration or on reset. */ void hw_watchpoint_update_all(ARMCPU *cpu); -/* Update a QEMU breakpoint based on the information the guest has set in the +/* + * Update a QEMU breakpoint based on the information the guest has set in the * DBGBCR_EL1 and DBGBVR_EL1 registers. */ void hw_breakpoint_update(ARMCPU *cpu, int n); -/* Update the QEMU breakpoints for every guest breakpoint. This does a +/* + * Update the QEMU breakpoints for every guest breakpoint. This does a * complete delete-and-reinstate of the QEMU breakpoint list and so is * suitable for use after migration or on reset. */ @@ -284,7 +289,8 @@ void hw_breakpoint_update_all(ARMCPU *cpu); /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); -/* Adjust addresses (in BE32 mode) before testing against watchpoint +/* + * Adjust addresses (in BE32 mode) before testing against watchpoint * addresses. */ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);