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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id c20sm4630759eje.59.2021.02.26.01.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 01:32:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v5 12/13] target/mips: Introduce mxu_translate_init() helper Date: Fri, 26 Feb 2021 10:31:09 +0100 Message-Id: <20210226093111.3865906-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226093111.3865906-1-f4bug@amsat.org> References: <20210226093111.3865906-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper. Make it public and replace !TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to elide this code at preprocessing time. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.h | 1 + target/mips/translate.c | 28 ++++++++++++++++------------ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index a5c49f1ee22..a807b3d2566 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -179,6 +179,7 @@ extern TCGv bcond; void msa_translate_init(void); /* MXU */ +void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); /* decodetree generated */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 84948ab9ce0..da6825c2fec 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] = { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", }; -#endif + +void mxu_translate_init(void) +{ + for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR = tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); +} +#endif /* !TARGET_MIPS64 */ /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) @@ -28047,18 +28060,9 @@ void mips_tcg_init(void) cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval), "llval"); -#if !defined(TARGET_MIPS64) - for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { - mxu_gpr[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, - active_tc.mxu_gpr[i]), - mxuregnames[i]); + if (TARGET_LONG_BITS == 32) { + mxu_translate_init(); } - - mxu_CR = tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.mxu_cr), - mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); -#endif /* !TARGET_MIPS64 */ } void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,