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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id x17sm13176654edq.42.2021.02.22.14.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 05/10] target/mips: Extract decode_ase_mxu() from decode_opc_mxu() Date: Mon, 22 Feb 2021 23:38:56 +0100 Message-Id: <20210222223901.2792336-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To easily convert MXU code to decodetree, extract decode_ase_mxu() from decode_opc_mxu(), making it return a boolean. We will keep decode_opc_mxu() in the translate.c unit because it calls gen_arith(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 45 ++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9e875fa4a25..6f853fcdcce 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25777,34 +25777,18 @@ static void decode_opc_mxu__pool19(DisasContext *ctx) } } -/* - * Main MXU decoding function - */ -static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) +static bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode = extract32(insn, 0, 6); - if (opcode == OPC__MXU_MUL) { - uint32_t rs, rt, rd, op1; - - rs = extract32(insn, 21, 5); - rt = extract32(insn, 16, 5); - rd = extract32(insn, 11, 5); - op1 = MASK_SPECIAL2(insn); - - gen_arith(ctx, op1, rd, rs, rt); - - return; - } - if (opcode == OPC_MXU_S32M2I) { gen_mxu_s32m2i(ctx); - return; + return true; } if (opcode == OPC_MXU_S32I2M) { gen_mxu_s32i2m(ctx); - return; + return true; } { @@ -25845,6 +25829,29 @@ static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) gen_set_label(l_exit); tcg_temp_free(t_mxu_cr); } + + return true; +} + +/* + * Main MXU decoding function + */ +static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) +{ + if (extract32(insn, 0, 6) == OPC__MXU_MUL) { + uint32_t rs, rt, rd, op1; + + rs = extract32(insn, 21, 5); + rt = extract32(insn, 16, 5); + rd = extract32(insn, 11, 5); + op1 = MASK_SPECIAL2(insn); + + gen_arith(ctx, op1, rd, rs, rt); + + return; + } + + decode_ase_mxu(ctx, insn); } #endif /* !defined(TARGET_MIPS64) */