diff mbox series

[3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

Message ID 20210215215819.1142-4-rebecca@nuviainc.com
State New
Headers show
Series target/arm: Add support for FEAT_SSBS | expand

Commit Message

Rebecca Cran Feb. 15, 2021, 9:58 p.m. UTC 
Enable FEAT_SSBS for the "max" 32-bit CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Richard Henderson Feb. 16, 2021, 12:20 a.m. UTC | #1 
On 2/15/21 1:58 PM, Rebecca Cran wrote:
> Enable FEAT_SSBS for the "max" 32-bit CPU.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
>  target/arm/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cf6c056c50f..88a6b183d325 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2206,6 +2206,10 @@  static void arm_max_initfn(Object *obj)
         t = cpu->isar.id_pfr0;
         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
         cpu->isar.id_pfr0 = t;
+
+        t = cpu->isar.id_pfr2;
+        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+        cpu->isar.id_mfr2 = t;
     }
 #endif
 }