Message ID | 20210209193018.31339-7-mark.cave-ayland@ilande.co.uk |
---|---|
State | New |
Headers | show |
Series | esp: consolidate PDMA transfer buffers and other fixes | expand |
Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > Move the trace event to the end of the function so that it correctly reports > the returned value if it doesn't come directly from the rregs array. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > hw/scsi/esp.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c > index 9951472ee6..c36cb0f238 100644 > --- a/hw/scsi/esp.c > +++ b/hw/scsi/esp.c > @@ -595,9 +595,8 @@ static void parent_esp_reset(ESPState *s, int irq, int level) > > uint64_t esp_reg_read(ESPState *s, uint32_t saddr) > { > - uint32_t old_val; > + uint32_t val; > > - trace_esp_mem_readb(saddr, s->rregs[saddr]); > switch (saddr) { > case ESP_FIFO: > if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { > @@ -612,13 +611,14 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) > s->ti_rptr = 0; > s->ti_wptr = 0; > } > + val = s->rregs[ESP_FIFO]; > break; > case ESP_RINTR: > /* > * Clear sequence step, interrupt register and all status bits > * except TC > */ > - old_val = s->rregs[ESP_RINTR]; > + val = s->rregs[ESP_RINTR]; > s->rregs[ESP_RINTR] = 0; > s->rregs[ESP_RSTAT] &= ~STAT_TC; > s->rregs[ESP_RSEQ] = SEQ_CD; > @@ -627,16 +627,22 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) > esp_report_command_complete(s, s->deferred_status); > s->deferred_complete = false; > } > - return old_val; > + break; > case ESP_TCHI: > /* Return the unique id if the value has never been written */ > if (!s->tchi_written) { > - return s->chip_id; > + val = s->chip_id; > + } else { > + val = s->rregs[saddr]; > } > + break; > default: > + val = s->rregs[saddr]; > break; > } > - return s->rregs[saddr]; > + > + trace_esp_mem_readb(saddr, val); > + return val; > } > > void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) > Reviewed-by: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 9951472ee6..c36cb0f238 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -595,9 +595,8 @@ static void parent_esp_reset(ESPState *s, int irq, int level) uint64_t esp_reg_read(ESPState *s, uint32_t saddr) { - uint32_t old_val; + uint32_t val; - trace_esp_mem_readb(saddr, s->rregs[saddr]); switch (saddr) { case ESP_FIFO: if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { @@ -612,13 +611,14 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) s->ti_rptr = 0; s->ti_wptr = 0; } + val = s->rregs[ESP_FIFO]; break; case ESP_RINTR: /* * Clear sequence step, interrupt register and all status bits * except TC */ - old_val = s->rregs[ESP_RINTR]; + val = s->rregs[ESP_RINTR]; s->rregs[ESP_RINTR] = 0; s->rregs[ESP_RSTAT] &= ~STAT_TC; s->rregs[ESP_RSEQ] = SEQ_CD; @@ -627,16 +627,22 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) esp_report_command_complete(s, s->deferred_status); s->deferred_complete = false; } - return old_val; + break; case ESP_TCHI: /* Return the unique id if the value has never been written */ if (!s->tchi_written) { - return s->chip_id; + val = s->chip_id; + } else { + val = s->rregs[saddr]; } + break; default: + val = s->rregs[saddr]; break; } - return s->rregs[saddr]; + + trace_esp_mem_readb(saddr, val); + return val; } void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)