Message ID | 20210206232058.4209-1-elias-djossou.git@gmx.de |
---|---|
State | New |
Headers | show |
Series | Expose i386 model specific registers via HMP | expand |
Patchew URL: https://patchew.org/QEMU/20210206232058.4209-1-elias-djossou.git@gmx.de/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210206232058.4209-1-elias-djossou.git@gmx.de Subject: [PATCH] Expose i386 model specific registers via HMP === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20210206232058.4209-1-elias-djossou.git@gmx.de -> patchew/20210206232058.4209-1-elias-djossou.git@gmx.de Switched to a new branch 'test' 110d6be Expose i386 model specific registers via HMP === OUTPUT BEGIN === ERROR: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 82 lines checked Commit 110d6be24005 (Expose i386 model specific registers via HMP) has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20210206232058.4209-1-elias-djossou.git@gmx.de/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index 117ba25f91..d78c3e799d 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -893,3 +893,18 @@ SRST ``info replay`` Display the record/replay information: mode and the current icount. ERST + +#if defined(TARGET_I386) + { + .name = "msr-registers", + .args_type = "cpustate_all:-a", + .params = "[-a]", + .help = "show the cpu msr registers (-a: all - show msr register info for all cpus)", + .cmd = hmp_info_msr_registers, + }, +#endif + +SRST + ``info msr-registers`` + Show the cpu msr registers. +ERST diff --git a/include/monitor/hmp-target.h b/include/monitor/hmp-target.h index 60fc92722a..756102a773 100644 --- a/include/monitor/hmp-target.h +++ b/include/monitor/hmp-target.h @@ -49,5 +49,6 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict); void hmp_mce(Monitor *mon, const QDict *qdict); void hmp_info_local_apic(Monitor *mon, const QDict *qdict); void hmp_info_io_apic(Monitor *mon, const QDict *qdict); +void hmp_info_msr_registers(Monitor *mon, const QDict *qdict); #endif /* MONITOR_HMP_TARGET_H */ diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 1bc91442b1..b274c42bf3 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -736,3 +736,58 @@ void qmp_sev_inject_launch_secret(const char *packet_hdr, { sev_inject_launch_secret(packet_hdr, secret, gpa, errp); } + +static void x86_print_msr_registers(Monitor *mon, CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + monitor_printf(mon, + "MSR_IA32_SYSENTER_CS=%08x\n" + "MSR_IA32_SYSENTER_ESP=%016lx\n" + "MSR_IA32_SYSENTER_EIP=%016lx\n" + "MSR_STAR=%016lx\n", + env->sysenter_cs, + env->sysenter_esp, + env->sysenter_eip, + env->star); + +#ifdef TARGET_X86_64 + monitor_printf(mon, + "MSR_LSTAR=%016lx\n" + "MSR_CSTAR=%016lx\n" + "MSR_FMASK=%016lx\n" + "MSR_FSBASE=%016lx\n" + "MSR_GSBASE=%016lx\n" + "MSR_KERNELGSBASE=%016lx\n", + env->lstar, + env->cstar, + env->fmask, + env->segs[R_FS].base, + env->segs[R_GS].base, + env->kernelgsbase); +#endif + +} + +void hmp_info_msr_registers(Monitor *mon, const QDict *qdict) +{ + bool all_cpus = qdict_get_try_bool(qdict, "cpustate_all", false); + CPUState *cs; + + if (all_cpus) { + CPU_FOREACH(cs) { + monitor_printf(mon, "\nCPU#%d\n", cs->cpu_index); + x86_print_msr_registers(mon, cs); + } + } else { + cs = mon_get_cpu(mon); + + if (!cs) { + monitor_printf(mon, "No CPU available\n"); + return; + } + + x86_print_msr_registers(mon, cs); + } +}