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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id b10sm7050494pgh.15.2021.01.21.20.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 20:45:49 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v2 1/3] target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate. Date: Thu, 21 Jan 2021 21:45:35 -0700 Message-Id: <20210122044537.1823-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210122044537.1823-1-rebecca@nuviainc.com> References: <20210122044537.1823-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=rebecca@nuviainc.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" cpsr has been treated as being the same as spsr, but it isn't. Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate. Signed-off-by: Rebecca Cran --- target/arm/helper-a64.c | 4 +--- target/arm/helper.c | 4 ++-- target/arm/op_helper.c | 9 +-------- 3 files changed, 4 insertions(+), 13 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index c426c23d2c4e..0d2ac7bb7ee3 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1000,9 +1000,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) */ mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); cpsr_write(env, spsr, mask, CPSRWriteRaw); - if (!arm_singlestep_active(env)) { - env->uncached_cpsr &= ~PSTATE_SS; - } + env->pstate &= ~PSTATE_SS; aarch64_sync_64_to_32(env); if (spsr & CPSR_T) { diff --git a/target/arm/helper.c b/target/arm/helper.c index d2ead3fcbdbd..01b50316046b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9402,8 +9402,8 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero it now. */ - env->uncached_cpsr &= ~PSTATE_SS; - env->spsr = cpsr_read(env); + env->pstate &= ~PSTATE_SS; + env->spsr &= ~PSTATE_SS; /* Clear IT bits. */ env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 5e0f123043b5..65cb37d088f8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) uint32_t HELPER(cpsr_read)(CPUARMState *env) { - /* - * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr. - * This is convenient for populating SPSR_ELx, but must be - * hidden from aarch32 mode, where it is not visible. - * - * TODO: ARMv8.4-DIT -- need to move SS somewhere else. - */ - return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS); + return cpsr_read(env) & ~CPSR_EXEC; } void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)