| Message ID | 20210121190622.22000-12-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Convert CMSDK timer, watchdog, dualtimer to Clock framework | expand |
On 1/21/21 8:06 PM, Peter Maydell wrote: > Create two input clocks on the ARMSSE devices, one for the normal > MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the > appropriate devices. The old property-based clock frequency setting > will remain in place until conversion is complete. > > This is a migration compatibility break for machines mps2-an505, > mps2-an521, musca-a, musca-b1. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > include/hw/arm/armsse.h | 6 ++++++ > hw/arm/armsse.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On 19:06 Thu 21 Jan , Peter Maydell wrote: > Create two input clocks on the ARMSSE devices, one for the normal > MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the > appropriate devices. The old property-based clock frequency setting > will remain in place until conversion is complete. > > This is a migration compatibility break for machines mps2-an505, > mps2-an521, musca-a, musca-b1. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> > --- > include/hw/arm/armsse.h | 6 ++++++ > hw/arm/armsse.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h > index 4860a793f4b..bfa1e79c4fe 100644 > --- a/include/hw/arm/armsse.h > +++ b/include/hw/arm/armsse.h > @@ -37,6 +37,8 @@ > * per-CPU identity and control register blocks > * > * QEMU interface: > + * + Clock input "MAINCLK": clock for CPUs and most peripherals > + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals > * + QOM property "memory" is a MemoryRegion containing the devices provided > * by the board model. > * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock > @@ -103,6 +105,7 @@ > #include "hw/misc/armsse-mhu.h" > #include "hw/misc/unimp.h" > #include "hw/or-irq.h" > +#include "hw/clock.h" > #include "hw/core/split-irq.h" > #include "hw/cpu/cluster.h" > #include "qom/object.h" > @@ -209,6 +212,9 @@ struct ARMSSE { > > uint32_t nsccfg; > > + Clock *mainclk; > + Clock *s32kclk; > + > /* Properties */ > MemoryRegion *board_memory; > uint32_t exp_numirq; > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index d2ba0459c44..4349ce9bfdb 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -21,6 +21,7 @@ > #include "hw/arm/armsse.h" > #include "hw/arm/boot.h" > #include "hw/irq.h" > +#include "hw/qdev-clock.h" > > /* Format of the System Information block SYS_CONFIG register */ > typedef enum SysConfigFormat { > @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) > assert(info->sram_banks <= MAX_SRAM_BANKS); > assert(info->num_cpus <= SSE_MAX_CPUS); > > + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); > + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); > + > memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); > > for (i = 0; i < info->num_cpus; i++) { > @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > * map its upstream ends to the right place in the container. > */ > qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { > return; > } > @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > &error_abort); > > qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { > return; > } > @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > &error_abort); > > qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { > return; > } > @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > * 0x4002f000: S32K timer > */ > qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); > + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { > return; > } > @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); > > qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); > + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { > return; > } > @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ > > qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { > return; > } > @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); > > qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { > return; > } > @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address, > > static const VMStateDescription armsse_vmstate = { > .name = "iotkit", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (VMStateField[]) { > + VMSTATE_CLOCK(mainclk, ARMSSE), > + VMSTATE_CLOCK(s32kclk, ARMSSE), > VMSTATE_UINT32(nsccfg, ARMSSE), > VMSTATE_END_OF_LIST() > } > -- > 2.20.1 > --
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 4860a793f4b..bfa1e79c4fe 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -37,6 +37,8 @@ * per-CPU identity and control register blocks * * QEMU interface: + * + Clock input "MAINCLK": clock for CPUs and most peripherals + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock @@ -103,6 +105,7 @@ #include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" +#include "hw/clock.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" #include "qom/object.h" @@ -209,6 +212,9 @@ struct ARMSSE { uint32_t nsccfg; + Clock *mainclk; + Clock *s32kclk; + /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d2ba0459c44..4349ce9bfdb 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -21,6 +21,7 @@ #include "hw/arm/armsse.h" #include "hw/arm/boot.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" /* Format of the System Information block SYS_CONFIG register */ typedef enum SysConfigFormat { @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) assert(info->sram_banks <= MAX_SRAM_BANKS); assert(info->num_cpus <= SSE_MAX_CPUS); + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); for (i = 0; i < info->num_cpus; i++) { @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * map its upstream ends to the right place in the container. */ qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; } @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; } @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; } @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * 0x4002f000: S32K timer */ qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; } @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; } @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; } @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; } @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address, static const VMStateDescription armsse_vmstate = { .name = "iotkit", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(mainclk, ARMSSE), + VMSTATE_CLOCK(s32kclk, ARMSSE), VMSTATE_UINT32(nsccfg, ARMSSE), VMSTATE_END_OF_LIST() }
Create two input clocks on the ARMSSE devices, one for the normal MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the appropriate devices. The old property-based clock frequency setting will remain in place until conversion is complete. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/armsse.h | 6 ++++++ hw/arm/armsse.c | 17 +++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-)