diff mbox series

[v2,07/12] hw/block/nvme: remove redundant zeroing of PMR registers

Message ID 20210118094705.56772-8-its@irrelevant.dk
State New
Headers show
Series hw/block/nvme: misc cmb/pmr patches and bump to v1.4 | expand

Commit Message

Klaus Jensen Jan. 18, 2021, 9:47 a.m. UTC 
From: Klaus Jensen <k.jensen@samsung.com>

The controller registers are initially zero. Remove the redundant
zeroing.

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
 hw/block/nvme.c | 35 -----------------------------------
 1 file changed, 35 deletions(-)

Comments

Minwoo Im Jan. 18, 2021, 12:55 p.m. UTC | #1 
On 21-01-18 10:47:00, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
> 
> The controller registers are initially zero. Remove the redundant
> zeroing.
> 
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> ---
>  hw/block/nvme.c | 35 -----------------------------------
>  1 file changed, 35 deletions(-)
> 
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index f3bea582b3c0..9ee9570bb65c 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -4179,43 +4179,8 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
>  
>  static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
>  {
> -    /* PMR Capabities register */
> -    n->bar.pmrcap = 0;
> -    NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
> -    NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
>      NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
> -    NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
> -    /* Turn on bit 1 support */

This comment says that PMRWBM [1]th bit is set to PMRCAP below :).

>      NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
> -    NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
> -    NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
> -
> -    /* PMR Control register */
> -    n->bar.pmrctl = 0;
> -    NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
> -
> -    /* PMR Status register */
> -    n->bar.pmrsts = 0;
> -    NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
> -    NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
> -    NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
> -    NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
> -
> -    /* PMR Elasticity Buffer Size register */
> -    n->bar.pmrebs = 0;
> -    NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
> -    NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
> -    NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
> -
> -    /* PMR Sustained Write Throughput register */
> -    n->bar.pmrswtp = 0;
> -    NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
> -    NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
> -
> -    /* PMR Memory Space Control register */
> -    n->bar.pmrmsc = 0;
> -    NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
> -    NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
>  
>      pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
>                       PCI_BASE_ADDRESS_SPACE_MEMORY |
> -- 
> 2.30.0
> 
>
Klaus Jensen Jan. 18, 2021, 1:02 p.m. UTC | #2 
On Jan 18 21:55, Minwoo Im wrote:
> On 21-01-18 10:47:00, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> > 
> > The controller registers are initially zero. Remove the redundant
> > zeroing.
> > 
> > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > ---
> >  hw/block/nvme.c | 35 -----------------------------------
> >  1 file changed, 35 deletions(-)
> > 
> > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > index f3bea582b3c0..9ee9570bb65c 100644
> > --- a/hw/block/nvme.c
> > +++ b/hw/block/nvme.c
> > @@ -4179,43 +4179,8 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
> >  
> >  static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
> >  {
> > -    /* PMR Capabities register */
> > -    n->bar.pmrcap = 0;
> > -    NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
> > -    NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
> >      NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
> > -    NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
> > -    /* Turn on bit 1 support */
> 
> This comment says that PMRWBM [1]th bit is set to PMRCAP below :).
> 

Thanks!
diff mbox series

Patch

diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index f3bea582b3c0..9ee9570bb65c 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -4179,43 +4179,8 @@  static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
 
 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
 {
-    /* PMR Capabities register */
-    n->bar.pmrcap = 0;
-    NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
-    NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
     NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
-    NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
-    /* Turn on bit 1 support */
     NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
-    NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
-    NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
-
-    /* PMR Control register */
-    n->bar.pmrctl = 0;
-    NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
-
-    /* PMR Status register */
-    n->bar.pmrsts = 0;
-    NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
-    NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
-    NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
-    NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
-
-    /* PMR Elasticity Buffer Size register */
-    n->bar.pmrebs = 0;
-    NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
-    NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
-    NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
-
-    /* PMR Sustained Write Throughput register */
-    n->bar.pmrswtp = 0;
-    NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
-    NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
-
-    /* PMR Memory Space Control register */
-    n->bar.pmrmsc = 0;
-    NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
-    NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
 
     pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
                      PCI_BASE_ADDRESS_SPACE_MEMORY |