Message ID | 20201218060114.3591217-9-alistair.francis@wdc.com |
---|---|
State | New |
Headers | show
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17 Dec 2020 21:46:37 -0800 IronPort-SDR: 8zSAi6fSEjxGSn2+BAfdlHEUqqolX7YBcamNzAmWZq7zh9RpNlqRjpo9GIRrQcPvWXy2cL3/hD 7DYV7nS2T6xgySXkCf6lFMIIt57HyGG2JtzIZz2MnbARST5UcUSPjPatV04u5O1TGu7Flu2Srh ZHhKHh+EuR1WbI3ksvDeG5Dpl8AVk0HX2A3lZ2cJeJhIrNSNqu5tKpm6OEyJytjJPUVxXaBOUa K2Op5BbVKRi7iJjocsIe8b9F179G4cF+6B8j9xjg9wbp3Q2aQemVjpzOySb+tcGV2rSRkO3SCs HYQ= WDCIronportException: Internal Received: from 6hj08h2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.68]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Dec 2020 22:01:20 -0800 From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Date: Thu, 17 Dec 2020 22:00:59 -0800 Message-Id: <20201218060114.3591217-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218060114.3591217-1-alistair.francis@wdc.com> References: <20201218060114.3591217-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=614e9c0eb=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Palmer Dabbelt <palmerdabbelt@google.com>, alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>, Alistair Francis <alistair.francis@wdc.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
[PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
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diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))