diff mbox series

[v10,25/32] cpu: move do_unaligned_access to tcg_ops

Message ID 20201210121226.19822-26-cfontana@suse.de
State New
Headers show
Series i386 cleanup | expand

Commit Message

Claudio Fontana Dec. 10, 2020, 12:12 p.m. UTC 
make it consistently SOFTMMU-only.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 include/hw/core/cpu.h           | 17 +++--------------
 include/hw/core/tcg-cpu-ops.h   |  7 +++++++
 target/alpha/cpu.c              |  2 +-
 target/arm/cpu.c                |  2 +-
 target/hppa/cpu.c               |  4 +++-
 target/microblaze/cpu.c         |  2 +-
 target/mips/cpu.c               |  3 ++-
 target/nios2/cpu.c              |  2 +-
 target/riscv/cpu.c              |  2 +-
 target/s390x/cpu.c              |  2 +-
 target/sh4/cpu.c                |  2 +-
 target/sparc/cpu.c              |  2 +-
 target/xtensa/cpu.c             |  2 +-
 target/ppc/translate_init.c.inc |  2 +-
 14 files changed, 25 insertions(+), 26 deletions(-)

Comments

Philippe Mathieu-Daudé Dec. 10, 2020, 1:01 p.m. UTC | #1 
On 12/10/20 1:12 PM, Claudio Fontana wrote:
> make it consistently SOFTMMU-only.
> 
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  include/hw/core/cpu.h           | 17 +++--------------
>  include/hw/core/tcg-cpu-ops.h   |  7 +++++++
>  target/alpha/cpu.c              |  2 +-
>  target/arm/cpu.c                |  2 +-
>  target/hppa/cpu.c               |  4 +++-
>  target/microblaze/cpu.c         |  2 +-
>  target/mips/cpu.c               |  3 ++-
>  target/nios2/cpu.c              |  2 +-
>  target/riscv/cpu.c              |  2 +-
>  target/s390x/cpu.c              |  2 +-
>  target/sh4/cpu.c                |  2 +-
>  target/sparc/cpu.c              |  2 +-
>  target/xtensa/cpu.c             |  2 +-
>  target/ppc/translate_init.c.inc |  2 +-
>  14 files changed, 25 insertions(+), 26 deletions(-)
...

> -#ifdef CONFIG_SOFTMMU
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
>  static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
>                                          MMUAccessType access_type,
>                                          int mmu_idx, uintptr_t retaddr)
>  {
>      CPUClass *cc = CPU_GET_CLASS(cpu);
>  
> -    cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
> +    cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
>  }
> -#ifdef CONFIG_TCG
>  static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>                                            vaddr addr, unsigned size,
>                                            MMUAccessType access_type,
> @@ -858,10 +850,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>                                            mmu_idx, attrs, response, retaddr);
>      }
>  }
> -#endif /* CONFIG_TCG */
> -#endif /* CONFIG_SOFTMMU */
> -
> -#endif /* NEED_CPU_H */
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>  
>  /**
>   * cpu_set_pc:
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 3cc2733410..bac0165db6 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -50,6 +50,13 @@ typedef struct TcgCpuOperations {
>                                    unsigned size, MMUAccessType access_type,
>                                    int mmu_idx, MemTxAttrs attrs,
>                                    MemTxResult response, uintptr_t retaddr);
> +    /**
> +     * @do_unaligned_access: Callback for unaligned access handling, if
> +     * the target defines #TARGET_ALIGNED_ONLY.
> +     */
> +    void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
> +                                MMUAccessType access_type,
> +                                int mmu_idx, uintptr_t retaddr);

Similarly to previous patch, don't we want to restrict this
to system-mode?

>  
>      /**
>       * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
Claudio Fontana Dec. 10, 2020, 1:14 p.m. UTC | #2 
On 12/10/20 2:01 PM, Philippe Mathieu-Daudé wrote:
> On 12/10/20 1:12 PM, Claudio Fontana wrote:
>> make it consistently SOFTMMU-only.
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>>  include/hw/core/cpu.h           | 17 +++--------------
>>  include/hw/core/tcg-cpu-ops.h   |  7 +++++++
>>  target/alpha/cpu.c              |  2 +-
>>  target/arm/cpu.c                |  2 +-
>>  target/hppa/cpu.c               |  4 +++-
>>  target/microblaze/cpu.c         |  2 +-
>>  target/mips/cpu.c               |  3 ++-
>>  target/nios2/cpu.c              |  2 +-
>>  target/riscv/cpu.c              |  2 +-
>>  target/s390x/cpu.c              |  2 +-
>>  target/sh4/cpu.c                |  2 +-
>>  target/sparc/cpu.c              |  2 +-
>>  target/xtensa/cpu.c             |  2 +-
>>  target/ppc/translate_init.c.inc |  2 +-
>>  14 files changed, 25 insertions(+), 26 deletions(-)
> ...
> 
>> -#ifdef CONFIG_SOFTMMU
>> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
>>  static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
>>                                          MMUAccessType access_type,
>>                                          int mmu_idx, uintptr_t retaddr)
>>  {
>>      CPUClass *cc = CPU_GET_CLASS(cpu);
>>  
>> -    cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
>> +    cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
>>  }
>> -#ifdef CONFIG_TCG
>>  static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>>                                            vaddr addr, unsigned size,
>>                                            MMUAccessType access_type,
>> @@ -858,10 +850,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>>                                            mmu_idx, attrs, response, retaddr);
>>      }
>>  }
>> -#endif /* CONFIG_TCG */
>> -#endif /* CONFIG_SOFTMMU */
>> -
>> -#endif /* NEED_CPU_H */
>> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>>  
>>  /**
>>   * cpu_set_pc:
>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>> index 3cc2733410..bac0165db6 100644
>> --- a/include/hw/core/tcg-cpu-ops.h
>> +++ b/include/hw/core/tcg-cpu-ops.h
>> @@ -50,6 +50,13 @@ typedef struct TcgCpuOperations {
>>                                    unsigned size, MMUAccessType access_type,
>>                                    int mmu_idx, MemTxAttrs attrs,
>>                                    MemTxResult response, uintptr_t retaddr);
>> +    /**
>> +     * @do_unaligned_access: Callback for unaligned access handling, if
>> +     * the target defines #TARGET_ALIGNED_ONLY.
>> +     */
>> +    void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
>> +                                MMUAccessType access_type,
>> +                                int mmu_idx, uintptr_t retaddr);
> 
> Similarly to previous patch, don't we want to restrict this
> to system-mode?

In theory yes, (and what about exec_interrupt..?)
but we need to triple check the targets, because they tend to set these unconditionally.

Same concern about CONFIG_USER_ONLY vs NEED_CPU_H / CONFIG_SOFTMMU, would use CONFIG_USER_ONLY for consistency with the other targets?



> 
>>  
>>      /**
>>       * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
>
Claudio Fontana Dec. 10, 2020, 1:18 p.m. UTC | #3 
On 12/10/20 2:14 PM, Claudio Fontana wrote:
> On 12/10/20 2:01 PM, Philippe Mathieu-Daudé wrote:
>> On 12/10/20 1:12 PM, Claudio Fontana wrote:
>>> make it consistently SOFTMMU-only.
>>>
>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>> ---
>>>  include/hw/core/cpu.h           | 17 +++--------------
>>>  include/hw/core/tcg-cpu-ops.h   |  7 +++++++
>>>  target/alpha/cpu.c              |  2 +-
>>>  target/arm/cpu.c                |  2 +-
>>>  target/hppa/cpu.c               |  4 +++-
>>>  target/microblaze/cpu.c         |  2 +-
>>>  target/mips/cpu.c               |  3 ++-
>>>  target/nios2/cpu.c              |  2 +-
>>>  target/riscv/cpu.c              |  2 +-
>>>  target/s390x/cpu.c              |  2 +-
>>>  target/sh4/cpu.c                |  2 +-
>>>  target/sparc/cpu.c              |  2 +-
>>>  target/xtensa/cpu.c             |  2 +-
>>>  target/ppc/translate_init.c.inc |  2 +-
>>>  14 files changed, 25 insertions(+), 26 deletions(-)
>> ...
>>
>>> -#ifdef CONFIG_SOFTMMU
>>> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
>>>  static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
>>>                                          MMUAccessType access_type,
>>>                                          int mmu_idx, uintptr_t retaddr)
>>>  {
>>>      CPUClass *cc = CPU_GET_CLASS(cpu);
>>>  
>>> -    cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
>>> +    cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
>>>  }
>>> -#ifdef CONFIG_TCG
>>>  static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>>>                                            vaddr addr, unsigned size,
>>>                                            MMUAccessType access_type,
>>> @@ -858,10 +850,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>>>                                            mmu_idx, attrs, response, retaddr);
>>>      }
>>>  }
>>> -#endif /* CONFIG_TCG */
>>> -#endif /* CONFIG_SOFTMMU */
>>> -
>>> -#endif /* NEED_CPU_H */
>>> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>>>  
>>>  /**
>>>   * cpu_set_pc:
>>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>>> index 3cc2733410..bac0165db6 100644
>>> --- a/include/hw/core/tcg-cpu-ops.h
>>> +++ b/include/hw/core/tcg-cpu-ops.h
>>> @@ -50,6 +50,13 @@ typedef struct TcgCpuOperations {
>>>                                    unsigned size, MMUAccessType access_type,
>>>                                    int mmu_idx, MemTxAttrs attrs,
>>>                                    MemTxResult response, uintptr_t retaddr);
>>> +    /**
>>> +     * @do_unaligned_access: Callback for unaligned access handling, if
>>> +     * the target defines #TARGET_ALIGNED_ONLY.
>>> +     */
>>> +    void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
>>> +                                MMUAccessType access_type,
>>> +                                int mmu_idx, uintptr_t retaddr);
>>
>> Similarly to previous patch, don't we want to restrict this
>> to system-mode?
> 
> In theory yes, (and what about exec_interrupt..?)

exec_interrupt: probably not.

> but we need to triple check the targets, because they tend to set these unconditionally.
> 
> Same concern about CONFIG_USER_ONLY vs NEED_CPU_H / CONFIG_SOFTMMU, would use CONFIG_USER_ONLY for consistency with the other targets?
> 
> 
> 
>>
>>>  
>>>      /**
>>>       * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
>>
>
diff mbox series

Patch

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0c6c17fb48..db54223983 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -87,8 +87,6 @@  struct TranslationBlock;
  * @parse_features: Callback to parse command line arguments.
  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  * @has_work: Callback for checking if there is work to do.
- * @do_unaligned_access: Callback for unaligned access handling, if
- * the target defines #TARGET_ALIGNED_ONLY.
  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  * runtime configurable endianness is currently big-endian. Non-configurable
  * CPUs can use the default implementation of this method. This method should
@@ -154,9 +152,6 @@  struct CPUClass {
 
     int reset_dump_flags;
     bool (*has_work)(CPUState *cpu);
-    void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
-                                MMUAccessType access_type,
-                                int mmu_idx, uintptr_t retaddr);
     bool (*virtio_is_big_endian)(CPUState *cpu);
     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
                            uint8_t *buf, int len, bool is_write);
@@ -831,18 +826,15 @@  CPUState *cpu_by_arch_id(int64_t id);
 
 void cpu_interrupt(CPUState *cpu, int mask);
 
-#ifdef NEED_CPU_H
-
-#ifdef CONFIG_SOFTMMU
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
                                         MMUAccessType access_type,
                                         int mmu_idx, uintptr_t retaddr)
 {
     CPUClass *cc = CPU_GET_CLASS(cpu);
 
-    cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+    cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
 }
-#ifdef CONFIG_TCG
 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
                                           vaddr addr, unsigned size,
                                           MMUAccessType access_type,
@@ -858,10 +850,7 @@  static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
                                           mmu_idx, attrs, response, retaddr);
     }
 }
-#endif /* CONFIG_TCG */
-#endif /* CONFIG_SOFTMMU */
-
-#endif /* NEED_CPU_H */
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
 
 /**
  * cpu_set_pc:
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 3cc2733410..bac0165db6 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -50,6 +50,13 @@  typedef struct TcgCpuOperations {
                                   unsigned size, MMUAccessType access_type,
                                   int mmu_idx, MemTxAttrs attrs,
                                   MemTxResult response, uintptr_t retaddr);
+    /**
+     * @do_unaligned_access: Callback for unaligned access handling, if
+     * the target defines #TARGET_ALIGNED_ONLY.
+     */
+    void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+                                MMUAccessType access_type,
+                                int mmu_idx, uintptr_t retaddr);
 
     /**
      * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 3e651b246f..0b5f5a78e3 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -225,7 +225,7 @@  static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
     cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
-    cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
     dc->vmsd = &vmstate_alpha_cpu;
 #endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5e9202ed86..9a8c1dc2e1 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2266,9 +2266,9 @@  static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
     cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
-    cc->do_unaligned_access = arm_cpu_do_unaligned_access;
 #if !defined(CONFIG_USER_ONLY)
     cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
+    cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
     cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
     cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index cce6ae6213..0985b3661f 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -70,6 +70,7 @@  static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
     info->print_insn = print_insn_hppa;
 }
 
+#ifndef CONFIG_USER_ONLY
 static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
                                          MMUAccessType access_type,
                                          int mmu_idx, uintptr_t retaddr)
@@ -86,6 +87,7 @@  static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 
     cpu_loop_exit_restore(cs, retaddr);
 }
+#endif /* CONFIG_USER_ONLY */
 
 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
 {
@@ -149,9 +151,9 @@  static void hppa_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
     cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
+    cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
     dc->vmsd = &vmstate_hppa_cpu;
 #endif
-    cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
     cc->disas_set_info = hppa_cpu_disas_set_info;
     cc->tcg_ops.initialize = hppa_translate_init;
 
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index fa57a324dc..395f4a300f 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -318,7 +318,6 @@  static void mb_cpu_class_init(ObjectClass *oc, void *data)
     cc->class_by_name = mb_cpu_class_by_name;
     cc->has_work = mb_cpu_has_work;
     cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
-    cc->do_unaligned_access = mb_cpu_do_unaligned_access;
     cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
     cc->dump_state = mb_cpu_dump_state;
     cc->set_pc = mb_cpu_set_pc;
@@ -328,6 +327,7 @@  static void mb_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
     cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
+    cc->tcg_ops.do_unaligned_access = mb_cpu_do_unaligned_access;
     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
     dc->vmsd = &vmstate_mb_cpu;
 #endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 259bb791f7..236d0d707b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -239,7 +239,6 @@  static void mips_cpu_class_init(ObjectClass *c, void *data)
     cc->gdb_read_register = mips_cpu_gdb_read_register;
     cc->gdb_write_register = mips_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
-    cc->do_unaligned_access = mips_cpu_do_unaligned_access;
     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_mips_cpu;
 #endif
@@ -252,6 +251,8 @@  static void mips_cpu_class_init(ObjectClass *c, void *data)
 #ifndef CONFIG_USER_ONLY
     cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
     cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+    cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
+
 #endif /* CONFIG_USER_ONLY */
 #endif /* CONFIG_TCG */
 
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 2b959f0e49..059eea8c94 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -199,7 +199,7 @@  static void nios2_cpu_class_init(ObjectClass *oc, void *data)
     cc->disas_set_info = nios2_cpu_disas_set_info;
     cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
-    cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = nios2_cpu_do_unaligned_access;
     cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
 #endif
     cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7dfd8d7339..e5626862c2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,7 +556,7 @@  static void riscv_cpu_class_init(ObjectClass *c, void *data)
     cc->disas_set_info = riscv_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
     cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
-    cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
     /* For now, mark unmigratable: */
     cc->vmsd = &vmstate_riscv_cpu;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index b838bd61a4..86f654fd6b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -507,7 +507,7 @@  static void s390_cpu_class_init(ObjectClass *oc, void *data)
 #ifdef CONFIG_TCG
     cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
     cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
-    cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = s390x_cpu_do_unaligned_access;
 #endif
 #endif
     cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ff835d4bc1..fbd5f42675 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -227,7 +227,7 @@  static void superh_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_write_register = superh_cpu_gdb_write_register;
     cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
-    cc->do_unaligned_access = superh_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = superh_cpu_do_unaligned_access;
     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 #endif
     cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 009d0f07c3..3b53ef2390 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -874,7 +874,7 @@  static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
     cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
-    cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
     cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_sparc_cpu;
 #endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index fc52fde696..4b6381569f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -203,7 +203,7 @@  static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_stop_before_watchpoint = true;
     cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
 #ifndef CONFIG_USER_ONLY
-    cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
+    cc->tcg_ops.do_unaligned_access = xtensa_cpu_do_unaligned_access;
     cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
     cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
 #endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 0471da0d08..18ce389947 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10913,7 +10913,6 @@  static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     cc->set_pc = ppc_cpu_set_pc;
     cc->gdb_read_register = ppc_cpu_gdb_read_register;
     cc->gdb_write_register = ppc_cpu_gdb_write_register;
-    cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
 #ifndef CONFIG_USER_ONLY
     cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_ppc_cpu;
@@ -10950,6 +10949,7 @@  static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 #ifndef CONFIG_USER_ONLY
     cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
     cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+    cc->tcg_ops.do_unaligned_access = ppc_cpu_do_unaligned_access;
 #endif /* !CONFIG_USER_ONLY */
 #endif /* CONFIG_TCG */