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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id be6sm15474616edb.29.2020.12.07.15.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 15:55:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/7] target/mips/translate: Add declarations for generic code Date: Tue, 8 Dec 2020 00:55:34 +0100 Message-Id: <20201207235539.4070364-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201207235539.4070364-1-f4bug@amsat.org> References: <20201207235539.4070364-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::644; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x644.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 33 ++++++++++++++++++++++++++++++++ target/mips/translate.c | 42 ++++++++++++----------------------------- 2 files changed, 45 insertions(+), 30 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index fcda1a99001..dbf7df7ba6d 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -10,6 +10,8 @@ #include "exec/translator.h" +#define MIPS_DEBUG_DISAS 0 + typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; @@ -47,4 +49,35 @@ typedef struct DisasContext { int gi; } DisasContext; +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +void generate_exception_end(DisasContext *ctx, int excp); +void gen_reserved_instruction(DisasContext *ctx); +void check_insn(DisasContext *ctx, uint64_t flags); +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); + +void gen_load_gpr(TCGv t, int reg); +void gen_store_gpr(TCGv t, int reg); + +extern TCGv bcond; + +#define LOG_DISAS(...) \ + do { \ + if (MIPS_DEBUG_DISAS) { \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ + } \ + } while (0) + +#define MIPS_INVAL(op) \ + do { \ + if (MIPS_DEBUG_DISAS) { \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ + ctx->base.pc_next, ctx->opcode, op, \ + ctx->opcode >> 26, ctx->opcode & 0x3F, \ + ((ctx->opcode >> 16) & 0x1F)); \ + } \ + } while (0) + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index d7f5a1e8d84..46aab26b868 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -41,11 +41,6 @@ #include "qemu/qemu-print.h" #include "translate.h" -#define MIPS_DEBUG_DISAS 0 - -/* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) - enum { /* indirect opcode tables */ OPC_SPECIAL = (0x00 << 26), @@ -2496,7 +2491,8 @@ enum { /* global register indices */ static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget, bcond; +static TCGv cpu_dspctrl, btarget; +TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -2609,26 +2605,8 @@ static const char * const mxuregnames[] = { }; #endif -#define LOG_DISAS(...) \ - do { \ - if (MIPS_DEBUG_DISAS) { \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ - } \ - } while (0) - -#define MIPS_INVAL(op) \ - do { \ - if (MIPS_DEBUG_DISAS) { \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ - ctx->base.pc_next, ctx->opcode, op, \ - ctx->opcode >> 26, ctx->opcode & 0x3F, \ - ((ctx->opcode >> 16) & 0x1F)); \ - } \ - } while (0) - /* General purpose registers moves. */ -static inline void gen_load_gpr(TCGv t, int reg) +void gen_load_gpr(TCGv t, int reg) { if (reg == 0) { tcg_gen_movi_tl(t, 0); @@ -2637,7 +2615,7 @@ static inline void gen_load_gpr(TCGv t, int reg) } } -static inline void gen_store_gpr(TCGv t, int reg) +void gen_store_gpr(TCGv t, int reg) { if (reg != 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); @@ -2782,11 +2760,16 @@ static inline void generate_exception(DisasContext *ctx, int excp) gen_helper_0e0i(raise_exception, excp); } -static inline void generate_exception_end(DisasContext *ctx, int excp) +void generate_exception_end(DisasContext *ctx, int excp) { generate_exception_err(ctx, excp, 0); } +void gen_reserved_instruction(DisasContext *ctx) +{ + generate_exception_end(ctx, EXCP_RI); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -3016,7 +2999,7 @@ static inline void check_dsp_r3(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, uint64_t flags) +void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { generate_exception_end(ctx, EXCP_RI); @@ -3393,8 +3376,7 @@ OP_LD_ATOMIC(lld, ld64); #endif #undef OP_LD_ATOMIC -static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, - int base, int offset) +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) { if (base == 0) { tcg_gen_movi_tl(addr, offset);