Message ID | 20201201133525.2866838-5-f4bug@amsat.org |
---|---|
State | New |
Headers | show |
Series | linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3E | expand |
On 12/1/20 7:35 AM, Philippe Mathieu-Daudé wrote: > +#define GET_FEATURE_REG_EQU(_reg, _mask, _val, _hwcap) \ > + do { \ > + if ((cpu->env._reg & (_mask)) == _val) { \ > + hwcaps |= _hwcap; \ > + } \ > + } while (0) > + > static uint32_t get_elf_hwcap(void) > { > MIPSCPU *cpu = MIPS_CPU(thread_cpu); > uint32_t hwcaps = 0; > > - GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); > + GET_FEATURE_REG_EQU(CP0_Config0, 7 << CP0C0_AR, 2, HWCAP_MIPS_R6); You'd need 2 << CP0C0_AR for the equality to match. Would it be better to have the shift as a separate argument? r~
On 12/1/20 6:36 PM, Richard Henderson wrote: > On 12/1/20 7:35 AM, Philippe Mathieu-Daudé wrote: >> +#define GET_FEATURE_REG_EQU(_reg, _mask, _val, _hwcap) \ >> + do { \ >> + if ((cpu->env._reg & (_mask)) == _val) { \ >> + hwcaps |= _hwcap; \ >> + } \ >> + } while (0) >> + >> static uint32_t get_elf_hwcap(void) >> { >> MIPSCPU *cpu = MIPS_CPU(thread_cpu); >> uint32_t hwcaps = 0; >> >> - GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); >> + GET_FEATURE_REG_EQU(CP0_Config0, 7 << CP0C0_AR, 2, HWCAP_MIPS_R6); > > You'd need 2 << CP0C0_AR for the equality to match. Oops... > Would it be better to have the shift as a separate argument? Yes, thanks! Phil.
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b7c6d30723a..73c1972183b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -995,17 +995,25 @@ enum { #define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \ do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0) +#define GET_FEATURE_REG_EQU(_reg, _mask, _val, _hwcap) \ + do { \ + if ((cpu->env._reg & (_mask)) == _val) { \ + hwcaps |= _hwcap; \ + } \ + } while (0) + static uint32_t get_elf_hwcap(void) { MIPSCPU *cpu = MIPS_CPU(thread_cpu); uint32_t hwcaps = 0; - GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); + GET_FEATURE_REG_EQU(CP0_Config0, 7 << CP0C0_AR, 2, HWCAP_MIPS_R6); GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA); return hwcaps; } +#undef GET_FEATURE_REG_EQU #undef GET_FEATURE_REG_SET #undef GET_FEATURE_INSN
ISA features are usually denoted in read-only bits from CPU registers. Add the GET_FEATURE_REG_EQU() macro which checks if a CPU register has bits set to a specific value. Use the macro to check the 'Architecture Revision' level of the Config0 register, which is '2' when the Release 6 ISA is implemented. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- linux-user/elfload.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)