[06/26] target/mips: Extract DSP helper definitions

Message ID	20201120210844.2625602-7-f4bug@amsat.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PATCH 06/26] target/mips: Extract DSP helper definitions Date: Fri, 20 Nov 2020 22:08:24 +0100 Message-Id: <20201120210844.2625602-7-f4bug@amsat.org> In-Reply-To: <20201120210844.2625602-1-f4bug@amsat.org> References: <20201120210844.2625602-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x441.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Fredrik Noring <noring@nocrew.org>, Craig Janeczek <jancraig@amazon.com>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= <f4bug@amsat.org>, Laurent Vivier <laurent@vivier.eu>, Paolo Bonzini <pbonzini@redhat.com>, Huacai Chen <chenhc@lemote.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Aurelien Jarno <aurelien@aurel32.net> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/mips: Explode 60% of the 32K-lines translate.c \| expand [00/26] target/mips: Explode 60% of the 32K-lines translate.c [01/26] target/mips: Extract FPU helpers to 'fpu_helper.h' [02/26] target/mips: Extract MSA helpers to mod-mips-msa_helper.c [03/26] target/mips: Extract MSA helper definitions [04/26] target/mips: Extract MSA translation routines [05/26] target/mips: Rename dsp_helper.c as mod-mips-dsp_helper.c [06/26] target/mips: Extract DSP helper definitions [07/26] target/mips: Extract DSP translation routines [08/26] target/mips: Extract Multi-Threading helper definitions [09/26] target/mips: Extract Code Compaction ASE translation routines [10/26] target/mips: Extract the microMIPS ISA helper definitions [11/26] target/mips: Extract the microMIPS ISA translation routines [12/26] target/mips: Extract nanoMIPS ISA translation routines [13/26] target/mips: Extract NEC Vr54xx helpers to vendor-vr54xx_helper.c [14/26] target/mips: Extract NEC Vr54xx helper definitions [15/26] target/mips: Extract NEC Vr54xx translation routines [16/26] target/mips: Rename lmmi_helper.c as loong-simd_helper.c [17/26] target/mips: Extract Loongson SIMD helper definitions [18/26] target/mips: Extract Loongson SIMD translation routines [19/26] target/mips: Extract Loongson EXTensions translation routines [20/26] target/mips: Extract XBurst Media eXtension Unit translation routines [21/26] target/mips: Make pipeline 1 multiply opcodes generic [22/26] target/mips: Extract Toshiba TXx9 translation routines [23/26] target/mips: Extract Toshiba TX79 multimedia translation routines [24/26] MAINTAINERS: Add entry for MIPS Loongson TCG [25/26] MAINTAINERS: Add entry for MIPS Ingenic Xburst TCG [26/26] MAINTAINERS: Add entry for MIPS Toshiba TCG

diff --git a/target/mips/helper.h b/target/mips/helper.h index a44f42c6201..bce869f3718 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -447,341 +447,8 @@ DEF_HELPER_FLAGS_2(pasubub, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_1(biadd, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(pmovmskb, TCG_CALL_NO_RWG_SE, i64, i64) -/*** MIPS DSP ***/ -/* DSP Arithmetic Sub-class insns */ -DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(modsub, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_NO_RWG_SE, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_NO_RWG_SE, tl, tl) -#endif -DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env) -DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env) -DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env) -DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env) -DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env) -#endif -DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_NO_RWG_SE, - tl, i32, tl, tl) -DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_NO_RWG_SE, - tl, i32, tl, tl) -DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(precr_sra_qh_pw, - TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw, - TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) -DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(precrq_rs_qh_pw, - TCG_CALL_NO_RWG_SE, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#endif -DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(precrqu_s_ob_qh, - TCG_CALL_NO_RWG_SE, tl, tl, tl, env) - -DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_NO_RWG_SE, tl, tl) -#endif -DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) -#endif -DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) -#endif - -/* DSP GPR-Based Shift Sub-class insns */ -DEF_HELPER_FLAGS_3(shll_qb, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(shll_ob, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(shll_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(shll_s_ph, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(shll_qh, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(shll_s_qh, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(shll_s_w, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(shll_pw, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(shll_s_pw, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_2(shrl_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shrl_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#endif -DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_2(shra_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#endif -DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_2(shra_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_r_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#endif - -/* DSP Multiply Sub-class insns */ -DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(muleu_s_qh_obl, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(muleu_s_qh_obr, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(mulq_rs_qh, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(muleq_s_pw_qhl, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(muleq_s_pw_qhr, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpau_h_obl, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(dpau_h_obr, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpsu_h_obl, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(dpsu_h_obr, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpa_w_qh, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpaq_s_w_qh, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dps_w_qh, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpsq_s_w_qh, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(mulsaq_s_w_qh, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpaq_sa_l_pw, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(dpsq_sa_l_pw, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(mulsaq_s_l_pw, 0, void, tl, tl, i32, env) -#endif -DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, i32, tl, tl, env) -DEF_HELPER_FLAGS_3(mul_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(mul_s_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(mulq_s_ph, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(mulq_s_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(mulq_rs_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, i32, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_4(maq_s_w_qhll, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_s_w_qhlr, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_s_w_qhrl, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_s_w_qhrr, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_sa_w_qhll, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_sa_w_qhlr, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_sa_w_qhrl, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_sa_w_qhrr, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_s_l_pwl, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(maq_s_l_pwr, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(dmadd, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(dmaddu, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env) -DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env) -#endif - -/* DSP Bit/Manipulation Sub-class insns */ -DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl) -#endif - -/* DSP Compare-Pick Sub-class insns */ -DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) -#endif - -/* DSP Accumulator and DSPControl Access Sub-class insns */ -DEF_HELPER_FLAGS_3(extr_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(extr_r_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(extr_rs_w, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dextr_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(dextr_r_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(dextr_rs_w, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(dextr_l, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(dextr_r_l, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(dextr_rs_l, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(extr_s_h, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dextr_s_h, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(extp, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(extpdp, 0, tl, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dextp, 0, tl, tl, tl, env) -DEF_HELPER_FLAGS_3(dextpdp, 0, tl, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(shilo, 0, void, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dshilo, 0, void, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(mthlip, 0, void, tl, tl, env) -#if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) -#endif -DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) -DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) - DEF_HELPER_3(cache, void, env, tl, i32) +#include "mod-mips-dsp_helper.h.inc" #include "mod-mips-msa_helper.h.inc" diff --git a/target/mips/mod-mips-dsp_helper.h.inc b/target/mips/mod-mips-dsp_helper.h.inc new file mode 100644 index 00000000000..83f188a697e --- /dev/null +++ b/target/mips/mod-mips-dsp_helper.h.inc @@ -0,0 +1,344 @@ +/* + * MIPS ASE DSP instruction emulation helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +/* DSP Arithmetic Sub-class insns */ +DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(modsub, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_NO_RWG_SE, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_NO_RWG_SE, tl, tl) +#endif +DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env) +#endif +DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_NO_RWG_SE, + tl, i32, tl, tl) +DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_NO_RWG_SE, + tl, i32, tl, tl) +DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precr_sra_qh_pw, + TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw, + TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precrq_rs_qh_pw, + TCG_CALL_NO_RWG_SE, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif +DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(precrqu_s_ob_qh, + TCG_CALL_NO_RWG_SE, tl, tl, tl, env) + +DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_NO_RWG_SE, tl, tl) +#endif +DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) +#endif +DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) +#endif + +/* DSP GPR-Based Shift Sub-class insns */ +DEF_HELPER_FLAGS_3(shll_qb, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(shll_ob, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(shll_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(shll_s_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(shll_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(shll_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(shll_s_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(shll_pw, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(shll_s_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(shrl_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shrl_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif +DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(shra_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif +DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(shra_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif + +/* DSP Multiply Sub-class insns */ +DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(muleu_s_qh_obl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleu_s_qh_obr, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(mulq_rs_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(muleq_s_pw_qhl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleq_s_pw_qhr, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpau_h_obl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dpau_h_obr, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpsu_h_obl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dpsu_h_obr, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpa_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpaq_s_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dps_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpsq_s_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(mulsaq_s_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpaq_sa_l_pw, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpsq_sa_l_pw, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(mulsaq_s_l_pw, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_3(mul_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mul_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mulq_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mulq_s_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mulq_rs_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(maq_s_w_qhll, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_w_qhlr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_w_qhrl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_w_qhrr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhll, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhlr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhrl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhrr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_l_pwl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_l_pwr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmadd, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmaddu, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env) +#endif + +/* DSP Bit/Manipulation Sub-class insns */ +DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl) +#endif + +/* DSP Compare-Pick Sub-class insns */ +DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif + +/* DSP Accumulator and DSPControl Access Sub-class insns */ +DEF_HELPER_FLAGS_3(extr_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(extr_r_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(extr_rs_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dextr_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_r_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_rs_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_l, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_r_l, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_rs_l, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(extr_s_h, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dextr_s_h, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(extp, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(extpdp, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dextp, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextpdp, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(shilo, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dshilo, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(mthlip, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)

[06/26] target/mips: Extract DSP helper definitions

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