Message ID | 20201119215617.29887-18-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/arm: Implement v8.1M and Cortex-M55 | expand |
On 11/19/20 3:56 PM, Peter Maydell wrote: > In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule > R_LLRP). (In previous versions of the architecture this was either > required or IMPDEF.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/m_helper.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 721b4b4896e..9cdc8a64c29 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -722,11 +722,15 @@ load_fail: * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are * secure); otherwise it targets the same security state as the * underlying exception. + * In v8.1M HardFaults from vector table fetch fails don't set FORCED. */ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { exc_secure = true; } - env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; + env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK; + if (!arm_feature(env, ARM_FEATURE_V8_1M)) { + env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; + } armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure); return false; }
In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule R_LLRP). (In previous versions of the architecture this was either required or IMPDEF.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/m_helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)