From patchwork Wed Nov 11 05:47:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 1397945 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CWDKl0RpQz9sRK for ; Wed, 11 Nov 2020 16:48:11 +1100 (AEDT) Received: from localhost ([::1]:40144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kcizI-000468-SN for incoming@patchwork.ozlabs.org; Wed, 11 Nov 2020 00:48:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kciys-0003zm-In for qemu-devel@nongnu.org; Wed, 11 Nov 2020 00:47:42 -0500 Received: from mga14.intel.com ([192.55.52.115]:60768) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kciyo-0008O5-Iy for qemu-devel@nongnu.org; Wed, 11 Nov 2020 00:47:42 -0500 IronPort-SDR: JvJW7b/Ikc8BiYB8tEMsv2dxEAY7xRJk9nAfA3nczk00PmmSLrNdi7qu2OY9KHh35vLAGzlbGo ms9e6TZFDNgg== X-IronPort-AV: E=McAfee;i="6000,8403,9801"; a="169314665" X-IronPort-AV: E=Sophos;i="5.77,468,1596524400"; d="scan'208";a="169314665" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2020 21:47:30 -0800 IronPort-SDR: oVe/Wk4TqaEHMmfD/p2icPCTIBTYLPxzYqSVjX5EkiygiMtDDOCxvbbNPlKd++0p4xBd5RH9lc SwATkUXdT5FA== X-IronPort-AV: E=Sophos;i="5.77,468,1596524400"; d="scan'208";a="308710400" Received: from hccoutan-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.131.159]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2020 21:47:29 -0800 From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH 05/25] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Date: Tue, 10 Nov 2020 21:47:04 -0800 Message-Id: <20201111054724.794888-6-ben.widawsky@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201111054724.794888-1-ben.widawsky@intel.com> References: <20201111054724.794888-1-ben.widawsky@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.115; envelope-from=ben.widawsky@intel.com; helo=mga14.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/11 00:47:28 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vishal Verma , Dan Williams , Ben Widawsky Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This implements all device MMIO up to the first capability .That includes the CXL Device Capabilities Array Register, as well as all of the CXL Device Capability Header Registers. The latter are filled in as they are implemented in the following patches. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-device-utils.c | 73 +++++++++++++++++++++++++++++++++++++++ hw/cxl/meson.build | 1 + 2 files changed, 74 insertions(+) diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index e69de29bb2..a391bb15c6 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -0,0 +1,73 @@ +/* + * CXL Utility library for devices + * + * Copyright(C) 2020 Intel Corporation. + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/cxl/cxl.h" + +static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size) +{ + CXLDeviceState *cxl_dstate = opaque; + + switch (size) { + case 4: + if (unlikely(offset & (sizeof(uint32_t) - 1))) { + qemu_log_mask(LOG_UNIMP, "Unaligned register read\n"); + return 0; + } + break; + case 8: + if (unlikely(offset & (sizeof(uint64_t) - 1))) { + qemu_log_mask(LOG_UNIMP, "Unaligned register read\n"); + return 0; + } + break; + } + + return ldn_le_p(cxl_dstate->caps_reg_state + offset, size); +} + +static const MemoryRegionOps caps_ops = { + .read = caps_reg_read, + .write = NULL, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 4, + .max_access_size = 8, + }, +}; + +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate) +{ + /* This will be a BAR, so needs to be rounded up to pow2 for PCI spec */ + memory_region_init( + &cxl_dstate->device_registers, obj, "device-registers", + pow2ceil(CXL_MAILBOX_REGISTERS_LENGTH + CXL_MAILBOX_REGISTERS_OFFSET)); + + memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate, + "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); + + memory_region_add_subregion(&cxl_dstate->device_registers, 0, + &cxl_dstate->caps); +} + +void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) +{ + uint32_t *cap_hdrs = cxl_dstate->caps_reg_state32; + const int cap_count = 0; + + /* CXL Device Capabilities Array Register */ + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1); + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count); +} diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build index 00c3876a0f..47154d6850 100644 --- a/hw/cxl/meson.build +++ b/hw/cxl/meson.build @@ -1,3 +1,4 @@ softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( 'cxl-component-utils.c', + 'cxl-device-utils.c', ))