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03 Nov 2020 07:19:36 -0800 IronPort-SDR: BhWFul50anFknOln8z3xVmSXYQfYpheF7gb0VhzdEZtK+WSB22u6ImU3VhUB0mstQ9vs3hrYn3 P9gLLJCetY0FQyp0BBK6o9Qi5i7hM3jgxFIyJkuU92lqqXnWMTJBTVpJBCIsCrgpkOyA99eKt3 v7EczKukGcS7WvAL9zLjPOpsZO45rXV89VmPRFTDdqfu3fiNM1N3C6yXIJ0mELw3yM2dg7b8BL P4TvFlXTs5VIRzvFPqtHMRRFWO0M5lePzW6YuEMfywOriGtW6GfgG3ZhSVf673m5maDSHn0KB2 oAQ= WDCIronportException: Internal Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Nov 2020 07:33:28 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Date: Tue, 3 Nov 2020 07:21:47 -0800 Message-Id: <20201103152150.2677566-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201103152150.2677566-1-alistair.francis@wdc.com> References: <20201103152150.2677566-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=569a91e0c=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 10:33:23 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Somehow HSS needs to access address 0 [1] for the DDR calibration data which is in the chipset's reserved memory. Let's map it. [1] See the config_copy() calls in various places in ddr_setup() in the HSS source codes. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 1 + hw/riscv/microchip_pfsoc.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 245c82db61..f34a6b3fd7 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -74,6 +74,7 @@ typedef struct MicrochipIcicleKitState { TYPE_MICROCHIP_ICICLE_KIT_MACHINE) enum { + MICROCHIP_PFSOC_RSVD0, MICROCHIP_PFSOC_DEBUG, MICROCHIP_PFSOC_E51_DTIM, MICROCHIP_PFSOC_BUSERR_UNIT0, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index bc908e07d9..44a84732ac 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -90,7 +90,8 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } microchip_pfsoc_memmap[] = { - [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, + [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, + [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, @@ -176,6 +177,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); const struct MemmapEntry *memmap = microchip_pfsoc_memmap; MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); MemoryRegion *envm_data = g_new(MemoryRegion, 1); @@ -195,6 +197,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); + /* Reserved Memory at address 0 */ + memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", + memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_RSVD0].base, + rsvd0_mem); + /* E51 DTIM */ memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);