| Message ID | 20201030151541.11976-1-remi@remlab.net |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/boot: fix SVE for EL3 direct kernel boot | expand |
On 10/30/20 8:15 AM, remi@remlab.net wrote: > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> > > When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so > that SVE will not trap to EL3. > > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> > --- > hw/arm/boot.c | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Fri, 30 Oct 2020 at 18:56, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 10/30/20 8:15 AM, remi@remlab.net wrote: > > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> > > > > When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so > > that SVE will not trap to EL3. > > > > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> > > --- > > hw/arm/boot.c | 3 +++ > > 1 file changed, 3 insertions(+) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Applied to target-arm.next, thanks. -- PMM
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3e9816af80..cf97600a91 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -742,6 +742,9 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_mte, cpu)) { env->cp15.scr_el3 |= SCR_ATA; } + if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cptr_el[3] |= CPTR_EZ; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: