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29 Oct 2020 07:11:44 -0700 IronPort-SDR: TKEONT9XzMA30PvXBAHMWMg2RyrMsunRJJUfXJ4up6Zz7NoRY3YEaqhrz9/60delWviMGhgoUM VMgD1pqMQvsh7mZiRQb8FfDN3AecuHtjUaXF2tHFvHiIsq6na2IHSgDT6ClbGJUkezPCfsn7B8 6pJAztyLOZ5DNDxpOkVFw8AvrNjffUGQR93vzssweJVgE6PxAw5+l6b//vIuMdivq8/YaZHxUE 7BdusxXKzFNwlif6i/4RaryncRcHg+s2Bs/BkWDI4QQz6wd6nEFP+GXUKPT3NmQnvrTO01+nDm kmI= WDCIronportException: Internal Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.131]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Oct 2020 07:25:30 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Date: Thu, 29 Oct 2020 07:13:51 -0700 Message-Id: <20201029141358.3102636-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201029141358.3102636-1-alistair.francis@wdc.com> References: <20201029141358.3102636-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=56447669b=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 10:25:26 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 5 +++++ hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 24 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 8bfc7e1a85..5b81e26241 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" +#include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; + MchpPfSoCDdrCfgState ddr_cfg; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -82,7 +85,9 @@ enum { MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_DDR_SGMII_PHY, MICROCHIP_PFSOC_EMMC_SD, + MICROCHIP_PFSOC_DDR_CFG, MICROCHIP_PFSOC_MMUART1, MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 6aac8497fc..3c504f7c03 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -15,6 +15,7 @@ * 4) Cadence eMMC/SDHC controller and an SD card connected to it * 5) SiFive Platform DMA (Direct Memory Access Controller) * 6) GEM (Gigabit Ethernet MAC Controller) + * 7) DMC (DDR Memory Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -103,7 +104,9 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, @@ -149,6 +152,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "dma-controller", &s->dma, TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, + TYPE_MCHP_PFSOC_DDR_SGMII_PHY); + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, + TYPE_MCHP_PFSOC_DDR_CFG); + object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); @@ -278,6 +286,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); + /* DDR SGMII PHY */ + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); + + /* DDR CFG */ + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, + memmap[MICROCHIP_PFSOC_DDR_CFG].base); + /* SDHCI */ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2df978fe8d..c8e50bde99 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -4,6 +4,7 @@ config IBEX config MICROCHIP_PFSOC bool select CADENCE_SDHCI + select MCHP_PFSOC_DMC select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT