| Message ID | 20201001160116.18095-1-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Make '-cpu max' have a 48-bit PA | expand |
On 10/1/20 11:01 AM, Peter Maydell wrote: > QEMU supports a 48-bit physical address range, but we don't currently > expose it in the '-cpu max' ID registers (you get the same range as > Cortex-A57, which is 44 bits). > > Set the ID_AA64MMFR0.PARange field to indicate 48 bits. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > I forget why I wanted this patch originally, it's been so long > since I wrote it, but it seems like a useful thing to allow -cpu max > to have a big PA range... > --- > target/arm/cpu64.c | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Were you by chance looking at some of the optional v8.2 extensions, one of which is a 52-bit VA, and noticed this nit? r~
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3c2b3d95993..3ba7f1675cc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -653,6 +653,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; + t = cpu->isar.id_aa64mmfr0; + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + cpu->isar.id_aa64mmfr0 = t; + t = cpu->isar.id_aa64mmfr1; t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
QEMU supports a 48-bit physical address range, but we don't currently expose it in the '-cpu max' ID registers (you get the same range as Cortex-A57, which is 44 bits). Set the ID_AA64MMFR0.PARange field to indicate 48 bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- I forget why I wanted this patch originally, it's been so long since I wrote it, but it seems like a useful thing to allow -cpu max to have a big PA range... --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+)