From patchwork Wed Sep 30 14:55:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 1374417 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=PtROxFUp; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C1fg93RXMz9sV1 for ; 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bh=Tqrz6vvOyDSCBuunJKKuWbLMvpvXJG8qPADR4RQyyHc=; b=PtROxFUpoh4zUNNwc1iVg4ItJqMF5WL6LH+ryVhQBvbr7iOCMIehQV52av63aqS9JJO1oJ HtvQmxVE1CXaxz6TV3tjkTuFIqNr7hnnZy6uMaG8omHDQhFHdjcbAprF5yDlIZ7tiqnJsi hzqPtosHNwtlsHHHg9JxDpQkwOIfRik= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-282-sfObWyOTOUy4BSh2jeCHPg-1; Wed, 30 Sep 2020 10:56:08 -0400 X-MC-Unique: sfObWyOTOUy4BSh2jeCHPg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 884691021203; Wed, 30 Sep 2020 14:56:07 +0000 (UTC) Received: from t480s.redhat.com (ovpn-113-220.ams2.redhat.com [10.36.113.220]) by smtp.corp.redhat.com (Postfix) with ESMTP id 20AB95C1C4; Wed, 30 Sep 2020 14:56:02 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v1 15/20] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE Date: Wed, 30 Sep 2020 16:55:18 +0200 Message-Id: <20200930145523.71087-16-david@redhat.com> In-Reply-To: <20200930145523.71087-1-david@redhat.com> References: <20200930145523.71087-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 00:31:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.469, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 3 ++ target/s390x/translate_vx.c.inc | 26 ++++++++--- target/s390x/vec_fpu_helper.c | 76 +++++++++++++++++++-------------- 3 files changed, 69 insertions(+), 36 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bee283e3d4..c2ded83669 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -331,8 +331,11 @@ DEF_HELPER_FLAGS_5(gvec_vfs32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfs128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) +DEF_HELPER_4(gvec_vftci32, void, ptr, cptr, env, i32) +DEF_HELPER_4(gvec_vftci32s, void, ptr, cptr, env, i32) DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32) DEF_HELPER_4(gvec_vftci64s, void, ptr, cptr, env, i32) +DEF_HELPER_4(gvec_vftci128, void, ptr, cptr, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc index 7d4811ccf7..6bd599b319 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -2991,16 +2991,32 @@ static DisasJumpType op_vftci(DisasContext *s, DisasOps *o) const uint16_t i3 = get_field(s, i3); const uint8_t fpf = get_field(s, m4); const uint8_t m5 = get_field(s, m5); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64; + const bool se = extract32(m5, 3, 1); + gen_helper_gvec_2_ptr *fn = NULL; - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { + switch (fpf) { + case FPF_SHORT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = se ? gen_helper_gvec_vftci32s : gen_helper_gvec_vftci32; + } + break; + case FPF_LONG: + fn = se ? gen_helper_gvec_vftci64s : gen_helper_gvec_vftci64; + break; + case FPF_EXT: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + fn = gen_helper_gvec_vftci128; + } + break; + default: + break; + } + + if (!fn || extract32(m5, 0, 3)) { gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (extract32(m5, 3, 1)) { - fn = gen_helper_gvec_vftci64s; - } gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn); set_cc_static(s); return DISAS_NEXT; diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index b7045e85d6..f18f0ae8e2 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -23,6 +23,9 @@ const float32 float32_ones = make_float32(-1u); const float64 float64_ones = make_float64(-1ull); const float128 float128_ones = make_float128(-1ull, -1ull); +const float32 float32_zeroes = make_float32(0); +const float64 float64_zeroes = make_float64(0); +const float128 float128_zeroes = make_float128(0, 0); #define VIC_INVALID 0x1 #define VIC_DIVBYZERO 0x2 @@ -782,39 +785,50 @@ void HELPER(gvec_vfs##BITS##s)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_FVS_S(32) DEF_GVEC_FVS_S(64) -static int vftci64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env, - bool s, uint16_t i3) -{ - int i, match = 0; - - for (i = 0; i < 2; i++) { - float64 a = s390_vec_read_element64(v2, i); - - if (float64_dcmask(env, a) & i3) { - match++; - s390_vec_write_element64(v1, i, -1ull); - } else { - s390_vec_write_element64(v1, i, 0); - } - if (s) { - break; - } - } - - if (match) { - return s || match == 2 ? 0 : 1; - } - return 3; +#define DEF_VFTCI(BITS) \ +static int vftci##BITS(S390Vector *v1, const S390Vector *v2, \ + CPUS390XState *env, bool s, uint16_t i3) \ +{ \ + int i, match = 0; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + float##BITS a = s390_vec_read_float##BITS(v2, i); \ + \ + if (float##BITS##_dcmask(env, a) & i3) { \ + match++; \ + s390_vec_write_float##BITS(v1, i, float##BITS##_ones); \ + } else { \ + s390_vec_write_float##BITS(v1, i, float##BITS##_zeroes); \ + } \ + if (s) { \ + break; \ + } \ + } \ + \ + if (match) { \ + return s || match == (128 / BITS) ? 0 : 1; \ + } \ + return 3; \ } +DEF_VFTCI(32) +DEF_VFTCI(64) +DEF_VFTCI(128) -void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - env->cc_op = vftci64(v1, v2, env, false, simd_data(desc)); +#define DEF_GVEC_VFTCI(BITS) \ +void HELPER(gvec_vftci##BITS)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + env->cc_op = vftci##BITS(v1, v2, env, false, simd_data(desc)); \ } +DEF_GVEC_VFTCI(32) +DEF_GVEC_VFTCI(64) +DEF_GVEC_VFTCI(128) -void HELPER(gvec_vftci64s)(void *v1, const void *v2, CPUS390XState *env, - uint32_t desc) -{ - env->cc_op = vftci64(v1, v2, env, true, simd_data(desc)); +#define DEF_GVEC_VFTCI_S(BITS) \ +void HELPER(gvec_vftci##BITS##s)(void *v1, const void *v2, CPUS390XState *env, \ + uint32_t desc) \ +{ \ + env->cc_op = vftci##BITS(v1, v2, env, true, simd_data(desc)); \ } +DEF_GVEC_VFTCI_S(32) +DEF_GVEC_VFTCI_S(64)