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[122.116.72.36]) by smtp.gmail.com with ESMTPSA id v8sm6003950pgg.58.2020.09.29.12.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 12:05:24 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v5 04/68] target/riscv: rvv-1.0: add sstatus VS field Date: Wed, 30 Sep 2020 03:03:39 +0800 Message-Id: <20200929190448.31116-5-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929190448.31116-1-frank.chang@sifive.com> References: <20200929190448.31116-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1033.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a65d3ab2b3..d77f790dec 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -425,6 +425,7 @@ #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ca04b44aea..05aca3243b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -423,7 +423,7 @@ static const target_ulong delegable_excps = (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS; static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP;