diff mbox series

[RFC,v5,31/68] target/riscv: rvv-1.0: iota instruction

Message ID	20200929190448.31116-32-frank.chang@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction Date: Wed, 30 Sep 2020 03:04:06 +0800 Message-Id: <20200929190448.31116-32-frank.chang@sifive.com> In-Reply-To: <20200929190448.31116-1-frank.chang@sifive.com> References: <20200929190448.31116-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1029.google.com Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	support vector extension v1.0 \| expand [RFC,v5,00/68] support vector extension v1.0 [RFC,v5,01/68] target/riscv: drop vector 0.7.1 and add 1.0 support [RFC,v5,02/68] target/riscv: Use FIELD_EX32() to extract wd field [RFC,v5,03/68] target/riscv: rvv-1.0: add mstatus VS field [RFC,v5,04/68] target/riscv: rvv-1.0: add sstatus VS field [RFC,v5,05/68] target/riscv: rvv-1.0: introduce writable misa.v field [RFC,v5,06/68] target/riscv: rvv-1.0: add translation-time vector context status [RFC,v5,07/68] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [RFC,v5,08/68] target/riscv: rvv-1.0: add vcsr register [RFC,v5,09/68] target/riscv: rvv-1.0: add vlenb register [RFC,v5,10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [RFC,v5,11/68] target/riscv: rvv-1.0: remove MLEN calculations [RFC,v5,12/68] target/riscv: rvv-1.0: add fractional LMUL [RFC,v5,13/68] target/riscv: rvv-1.0: add VMA and VTA [RFC,v5,14/68] target/riscv: rvv-1.0: update check functions [RFC,v5,15/68] target/riscv: introduce more imm value modes in translator functions [RFC,v5,16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function [RFC,v5,17/68] target/riscv: rvv-1.0: configure instructions [RFC,v5,18/68] target/riscv: rvv-1.0: stride load and store instructions [RFC,v5,19/68] target/riscv: rvv-1.0: index load and store instructions [RFC,v5,20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [RFC,v5,21/68] target/riscv: rvv-1.0: fault-only-first unit stride load [RFC,v5,22/68] target/riscv: rvv-1.0: amo operations [RFC,v5,23/68] target/riscv: rvv-1.0: load/store whole register instructions [RFC,v5,24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [RFC,v5,25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [RFC,v5,26/68] target/riscv: rvv-1.0: floating-point square-root instruction [RFC,v5,27/68] target/riscv: rvv-1.0: floating-point classify instructions [RFC,v5,28/68] target/riscv: rvv-1.0: mask population count instruction [RFC,v5,29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction [RFC,v5,30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions [RFC,v5,31/68] target/riscv: rvv-1.0: iota instruction [RFC,v5,32/68] target/riscv: rvv-1.0: element index instruction [RFC,v5,33/68] target/riscv: rvv-1.0: allow load element with sign-extended [RFC,v5,34/68] target/riscv: rvv-1.0: register gather instructions [RFC,v5,35/68] target/riscv: rvv-1.0: integer scalar move instructions [RFC,v5,36/68] target/riscv: rvv-1.0: floating-point move instruction [RFC,v5,37/68] target/riscv: rvv-1.0: floating-point scalar move instructions [RFC,v5,38/68] target/riscv: rvv-1.0: whole register move instructions [RFC,v5,39/68] target/riscv: rvv-1.0: integer extension instructions [RFC,v5,40/68] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [RFC,v5,41/68] target/riscv: rvv-1.0: single-width bit shift instructions [RFC,v5,42/68] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [RFC,v5,43/68] target/riscv: rvv-1.0: narrowing integer right shift instructions [RFC,v5,44/68] target/riscv: rvv-1.0: widening integer multiply-add instructions [RFC,v5,45/68] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [RFC,v5,46/68] target/riscv: rvv-1.0: integer comparison instructions [RFC,v5,47/68] target/riscv: rvv-1.0: floating-point compare instructions [RFC,v5,48/68] target/riscv: rvv-1.0: mask-register logical instructions [RFC,v5,49/68] target/riscv: rvv-1.0: slide instructions [RFC,v5,50/68] target/riscv: rvv-1.0: floating-point slide instructions [RFC,v5,51/68] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [RFC,v5,52/68] target/riscv: rvv-1.0: single-width floating-point reduction [RFC,v5,53/68] target/riscv: rvv-1.0: widening floating-point reduction instructions [RFC,v5,54/68] target/riscv: rvv-1.0: single-width scaling shift instructions [RFC,v5,55/68] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [RFC,v5,56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [RFC,v5,57/68] target/riscv: rvv-1.0: remove integer extract instruction [RFC,v5,58/68] target/riscv: rvv-1.0: floating-point min/max instructions [RFC,v5,59/68] target/riscv: introduce floating-point rounding mode enum [RFC,v5,60/68] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [RFC,v5,61/68] target/riscv: rvv-1.0: widening floating-point/integer type-convert [RFC,v5,62/68] target/riscv: add "set round to odd" rounding mode helper function [RFC,v5,63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [RFC,v5,64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [RFC,v5,65/68] target/riscv: gdb: modify gdb csr xml file to align with csr register map [RFC,v5,66/68] target/riscv: gdb: support vector registers for rv64 & rv32 [RFC,v5,67/68] target/riscv: implement vstart CSR [RFC,v5,68/68] target/riscv: trigger illegal instruction exception if frm is not valid

Commit Message

Frank Chang Sept. 29, 2020, 7:04 p.m. UTC

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn32.decode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0fed7c9e56..33b4612a69 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -607,7 +607,7 @@  vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
 vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m         010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
 vid_v           010110 . 00000 10001 010 ..... 1010111 @r1_vm
 vext_x_v        001100 1 ..... ..... 010 ..... 1010111 @r
 vmv_s_x         001101 1 00000 ..... 110 ..... 1010111 @r2