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[RFC,v2,03/10] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest

Message ID 20200917121449.3442059-4-liangpeng10@huawei.com
State New
Headers show
Series Support disable/enable CPU features for AArch64 | expand

Commit Message

Peng Liang Sept. 17, 2020, 12:14 p.m. UTC 
Some AArch64 CPU doesn't support AArch32 mode, AArch32 registers should
be 0.

Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 88bd9dd35da8..3a48bc4e4809 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6627,7 +6627,7 @@  static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
     ARMCPU *cpu = env_archcpu(env);
     uint64_t pfr1 = cpu->id_pfr1;
 
-    if (env->gicv3state) {
+    if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && env->gicv3state) {
         pfr1 |= 1 << 28;
     }
     return pfr1;