diff mbox series

[v2,50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE

Message ID 20200828141929.77854-51-richard.henderson@linaro.org
State New
Headers show
Series target/microblaze improvements | expand

Commit Message

Richard Henderson Aug. 28, 2020, 2:19 p.m. UTC
There's no reason to define MSR_EE_FLAG; we can just use the
original MSR_EE define.  Document the other flags copied into
tb_flags with iflag to reserve those bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h       | 4 +++-
 target/microblaze/translate.c | 4 ++--
 2 files changed, 5 insertions(+), 3 deletions(-)

Comments

Philippe Mathieu-Daudé Aug. 31, 2020, 9:09 p.m. UTC | #1
Le ven. 28 août 2020 16:42, Richard Henderson <richard.henderson@linaro.org>
a écrit :

> There's no reason to define MSR_EE_FLAG; we can just use the
> original MSR_EE define.  Document the other flags copied into
> tb_flags with iflag to reserve those bits.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

---
>  target/microblaze/cpu.h       | 4 +++-
>  target/microblaze/translate.c | 4 ++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 013858b8e0..594501e4e7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -254,7 +254,9 @@ struct CPUMBState {
>
>      /* Internal flags.  */
>  #define IMM_FLAG       4
> -#define MSR_EE_FLAG     (1 << 8)
> +/* MSR_EE               (1 << 8)  */
> +/* MSR_UM               (1 << 11) */
> +/* MSR_VM               (1 << 13) */
>  #define DRTI_FLAG      (1 << 16)
>  #define DRTE_FLAG      (1 << 17)
>  #define DRTB_FLAG      (1 << 18)
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 72541905ec..1f6731e0af 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -162,7 +162,7 @@ static void gen_goto_tb(DisasContext *dc, int n,
> target_ulong dest)
>   */
>  static bool trap_illegal(DisasContext *dc, bool cond)
>  {
> -    if (cond && (dc->tb_flags & MSR_EE_FLAG)
> +    if (cond && (dc->tb_flags & MSR_EE)
>          && dc->cpu->cfg.illegal_opcode_exception) {
>          gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP);
>      }
> @@ -178,7 +178,7 @@ static bool trap_userspace(DisasContext *dc, bool cond)
>      int mem_index = cpu_mmu_index(&dc->cpu->env, false);
>      bool cond_user = cond && mem_index == MMU_USER_IDX;
>
> -    if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) {
> +    if (cond_user && (dc->tb_flags & MSR_EE)) {
>          gen_raise_hw_excp(dc, ESR_EC_PRIVINSN);
>      }
>      return cond_user;
> --
> 2.25.1
>
>
>
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 013858b8e0..594501e4e7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -254,7 +254,9 @@  struct CPUMBState {
 
     /* Internal flags.  */
 #define IMM_FLAG	4
-#define MSR_EE_FLAG     (1 << 8)
+/* MSR_EE               (1 << 8)  */
+/* MSR_UM               (1 << 11) */
+/* MSR_VM               (1 << 13) */
 #define DRTI_FLAG	(1 << 16)
 #define DRTE_FLAG	(1 << 17)
 #define DRTB_FLAG	(1 << 18)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 72541905ec..1f6731e0af 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -162,7 +162,7 @@  static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
  */
 static bool trap_illegal(DisasContext *dc, bool cond)
 {
-    if (cond && (dc->tb_flags & MSR_EE_FLAG)
+    if (cond && (dc->tb_flags & MSR_EE)
         && dc->cpu->cfg.illegal_opcode_exception) {
         gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP);
     }
@@ -178,7 +178,7 @@  static bool trap_userspace(DisasContext *dc, bool cond)
     int mem_index = cpu_mmu_index(&dc->cpu->env, false);
     bool cond_user = cond && mem_index == MMU_USER_IDX;
 
-    if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) {
+    if (cond_user && (dc->tb_flags & MSR_EE)) {
         gen_raise_hw_excp(dc, ESR_EC_PRIVINSN);
     }
     return cond_user;