diff mbox series

[v2,31/76] target/microblaze: Remove DISAS_GNU

Message ID	20200828141929.77854-32-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v2 31/76] target/microblaze: Remove DISAS_GNU Date: Fri, 28 Aug 2020 07:18:44 -0700 Message-Id: <20200828141929.77854-32-richard.henderson@linaro.org> In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com Precedence: list Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/microblaze improvements \| expand [v2,00/76] target/microblaze improvements [v2,01/76] tests/tcg: Add microblaze to arches filter [v2,02/76] tests/tcg: Do not require FE_TOWARDZERO [v2,03/76] tests/tcg: Do not require FE_* exception bits [v2,04/76] target/microblaze: Tidy gdbstub [v2,05/76] target/microblaze: Split out PC from env->sregs [v2,06/76] target/microblaze: Split out MSR from env->sregs [v2,07/76] target/microblaze: Split out EAR from env->sregs [v2,08/76] target/microblaze: Split out ESR from env->sregs [v2,09/76] target/microblaze: Split out FSR from env->sregs [v2,10/76] target/microblaze: Split out BTR from env->sregs [v2,11/76] target/microblaze: Split out EDR from env->sregs [v2,12/76] target/microblaze: Split the cpu_SR array [v2,13/76] target/microblaze: Fix width of PC and BTARGET [v2,14/76] target/microblaze: Fix width of MSR [v2,15/76] target/microblaze: Fix width of ESR [v2,16/76] target/microblaze: Fix width of FSR [v2,17/76] target/microblaze: Fix width of BTR [v2,18/76] target/microblaze: Fix width of EDR [v2,19/76] target/microblaze: Remove cpu_ear [v2,20/76] target/microblaze: Tidy raising of exceptions [v2,21/76] target/microblaze: Mark raise_exception as noreturn [v2,22/76] target/microblaze: Remove helper_debug and env->debug [v2,23/76] target/microblaze: Rename env_* tcg variables to cpu_* [v2,24/76] target/microblaze: Tidy mb_tcg_init [v2,25/76] target/microblaze: Split out MSR[C] to its own variable [v2,26/76] target/microblaze: Use DISAS_NORETURN [v2,27/76] target/microblaze: Check singlestep_enabled in gen_goto_tb [v2,28/76] target/microblaze: Convert to DisasContextBase [v2,29/76] target/microblaze: Convert to translator_loop [v2,30/76] target/microblaze: Remove SIM_COMPAT [v2,31/76] target/microblaze: Remove DISAS_GNU [v2,32/76] target/microblaze: Remove empty D macros [v2,33/76] target/microblaze: Remove LOG_DIS [v2,34/76] target/microblaze: Ensure imm constant is always available [v2,35/76] target/microblaze: Add decodetree infrastructure [v2,36/76] target/microblaze: Convert dec_add to decodetree [v2,37/76] target/microblaze: Convert dec_sub to decodetree [v2,38/76] target/microblaze: Implement cmp and cmpu inline [v2,39/76] target/microblaze: Convert dec_pattern to decodetree [v2,40/76] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree [v2,41/76] target/microblaze: Convert dec_mul to decodetree [v2,42/76] target/microblaze: Convert dec_div to decodetree [v2,43/76] target/microblaze: Unwind properly when raising divide-by-zero [v2,44/76] target/microblaze: Convert dec_bit to decodetree [v2,45/76] target/microblaze: Convert dec_barrel to decodetree [v2,46/76] target/microblaze: Convert dec_imm to decodetree [v2,47/76] target/microblaze: Convert dec_fpu to decodetree [v2,48/76] target/microblaze: Fix cpu unwind for fpu exceptions [v2,49/76] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG [v2,50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE [v2,51/76] target/microblaze: Cache mem_index in DisasContext [v2,52/76] target/microblaze: Fix cpu unwind for stackprot [v2,53/76] target/microblaze: Convert dec_load and dec_store to decodetree [v2,54/76] target/microblaze: Assert no overlap in flags making up tb_flags [v2,55/76] target/microblaze: Move bimm to BIMM_FLAG [v2,56/76] target/microblaze: Fix no-op mb_cpu_transaction_failed [v2,57/76] target/microblaze: Store "current" iflags in insn_start [v2,58/76] tcg: Add tcg_get_insn_start_param [v2,59/76] target/microblaze: Use cc->do_unaligned_access [v2,60/76] target/microblaze: Replace clear_imm with tb_flags_to_set [v2,61/76] target/microblaze: Replace delayed_branch with tb_flags_to_set [v2,62/76] target/microblaze: Tidy mb_cpu_dump_state [v2,63/76] target/microblaze: Convert brk and brki to decodetree [v2,64/76] target/microblaze: Convert mbar to decodetree [v2,65/76] target/microblaze: Reorganize branching [v2,66/76] target/microblaze: Convert dec_br to decodetree [v2,67/76] target/microblaze: Convert dec_bcc to decodetree [v2,68/76] target/microblaze: Convert dec_rts to decodetree [v2,69/76] target/microblaze: Tidy do_rti, do_rtb, do_rte [v2,70/76] target/microblaze: Convert msrclr, msrset to decodetree [v2,71/76] target/microblaze: Convert dec_msr to decodetree [v2,72/76] target/microblaze: Convert dec_stream to decodetree [v2,73/76] target/microblaze: Remove last of old decoder [v2,74/76] target/microblaze: Remove cpu_R[0] [v2,75/76] target/microblaze: Add flags markup to some helpers [v2,76/76] target/microblaze: Reduce linux-user address space to 32-bit

Commit Message

Richard Henderson Aug. 28, 2020, 2:18 p.m. UTC

This is never used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 1 -
 1 file changed, 1 deletion(-)

diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a90e56a17f..6757720776 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -34,7 +34,6 @@ 
 #include "exec/log.h"
 
 
-#define DISAS_GNU 1
 #define DISAS_MB 1
 #if DISAS_MB
 #  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)