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[RFC,v2,1/3] target/mips/op_helper: Convert multiple if() to switch case

Message ID 20200813181527.22551-2-f4bug@amsat.org
State New
Headers show
Series [RFC,v2,1/3] target/mips/op_helper: Convert multiple if() to switch case | expand

Commit Message

Philippe Mathieu-Daudé Aug. 13, 2020, 6:15 p.m. UTC
The cache operation is encoded in bits [20:18] of the instruction.
The 'op' argument of helper_cache() contains the bits [20:16].
Extract the 3 bits and parse them using a switch case. This allow
us to handle multiple cache types (the cache type is encoded in
bits [17:16]).

Previously the if() block was only checking the D-Cache (Primary
Data or Unified Primary). Now we also handle the I-Cache (Primary
Instruction), S-Cache (Secondary) and T-Cache (Terciary).

Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/op_helper.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

Comments

Jiaxun Yang Aug. 14, 2020, 2:43 a.m. UTC | #1
在 2020/8/14 上午2:15, Philippe Mathieu-Daudé 写道:
> The cache operation is encoded in bits [20:18] of the instruction.
> The 'op' argument of helper_cache() contains the bits [20:16].
> Extract the 3 bits and parse them using a switch case. This allow
> us to handle multiple cache types (the cache type is encoded in
> bits [17:16]).
>
> Previously the if() block was only checking the D-Cache (Primary
> Data or Unified Primary). Now we also handle the I-Cache (Primary
> Instruction), S-Cache (Secondary) and T-Cache (Terciary).
>
> Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks~

> ---
>   target/mips/op_helper.c | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 9552b280e0..92c399d8d4 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -1574,15 +1574,22 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
>   void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
>   {
>   #ifndef CONFIG_USER_ONLY
> +    uint32_t cache_operation = extract32(op, 2, 3);
>       target_ulong index = addr & 0x1fffffff;
> -    if (op == 9) {
> +
> +    switch (cache_operation) {
> +    case 0b010:
>           /* Index Store Tag */
>           memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
>                                        MO_64, MEMTXATTRS_UNSPECIFIED);
> -    } else if (op == 5) {
> +        break;
> +    case 0b001:
>           /* Index Load Tag */
>           memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
>                                       MO_64, MEMTXATTRS_UNSPECIFIED);
> +        break;
> +    default:
> +        break;
>       }
>   #endif
>   }
diff mbox series

Patch

diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 9552b280e0..92c399d8d4 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1574,15 +1574,22 @@  void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
 {
 #ifndef CONFIG_USER_ONLY
+    uint32_t cache_operation = extract32(op, 2, 3);
     target_ulong index = addr & 0x1fffffff;
-    if (op == 9) {
+
+    switch (cache_operation) {
+    case 0b010:
         /* Index Store Tag */
         memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
                                      MO_64, MEMTXATTRS_UNSPECIFIED);
-    } else if (op == 5) {
+        break;
+    case 0b001:
         /* Index Load Tag */
         memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
                                     MO_64, MEMTXATTRS_UNSPECIFIED);
+        break;
+    default:
+        break;
     }
 #endif
 }