@@ -64,6 +64,14 @@ typedef struct I440FXState {
*/
#define I440FX_COREBOOT_RAM_SIZE 0x57
+/* Older I440FX machines (5.0 and older) not support i440FX-pcihost state
+ * migration, use some reserved INTEL 82441 configuration registers to
+ * save/restore i440FX-pcihost config register. Refer to [INTEL 440FX PCISET
+ * 82441FX PCI AND MEMORY CONTROLLER (PMC) AND 82442FX DATA BUS ACCELERATOR
+ * (DBX) Table 1. PMC Configuration Space]
+ */
+#define I440FX_PCI_HOST_CONFIG_REG 0x94
+
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i;
@@ -98,8 +106,30 @@ static void i440fx_write_config(PCIDevice *dev,
static int i440fx_post_load(void *opaque, int version_id)
{
PCII440FXState *d = opaque;
+ PCIDevice *dev;
+ PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path("/machine/i440fx", NULL),
+ TYPE_PCI_HOST_BRIDGE);
i440fx_update_memory_mappings(d);
+
+ if (!s->mig_enabled) {
+ dev = PCI_DEVICE(d);
+ s->config_reg = pci_get_long(&dev->config[I440FX_PCI_HOST_CONFIG_REG]);
+ }
+ return 0;
+}
+
+static int i440fx_pre_save(void *opaque)
+{
+ PCIDevice *dev = opaque;
+ PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path("/machine/i440fx", NULL),
+ TYPE_PCI_HOST_BRIDGE);
+ if (!s->mig_enabled) {
+ pci_set_long(&dev->config[I440FX_PCI_HOST_CONFIG_REG],
+ s->config_reg);
+ }
return 0;
}
@@ -107,6 +137,7 @@ static const VMStateDescription vmstate_i440fx = {
.name = "I440FX",
.version_id = 3,
.minimum_version_id = 3,
+ .pre_save = i440fx_pre_save,
.post_load = i440fx_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
@@ -43,6 +43,15 @@
#define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35)
+/* Older Q35 machines (5.0 and older) not support q35-pcihost state
+ * migration, use some reserved INTEL MCH configuration registers to
+ * save/restore q35-pcihost config register. Refer to [Intel 3 Series
+ * Chipset Family Datasheet Table 5-1. DRAM Controller Register Address
+ * Map (D0:F0)]
+ */
+#define Q35_PCI_HOST_CONFIG_REG 0x70
+
+
static void q35_host_realize(DeviceState *dev, Error **errp)
{
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
@@ -513,7 +522,27 @@ static void mch_update(MCHPCIState *mch)
static int mch_post_load(void *opaque, int version_id)
{
MCHPCIState *mch = opaque;
+ PCIDevice *dev;
+ PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path("/machine/q35", NULL),
+ TYPE_PCI_HOST_BRIDGE);
mch_update(mch);
+ if (!s->mig_enabled) {
+ dev = PCI_DEVICE(mch);
+ s->config_reg = pci_get_long(&dev->config[Q35_PCI_HOST_CONFIG_REG]);
+ }
+ return 0;
+}
+
+static int mch_pre_save(void *opaque)
+{
+ PCIDevice *dev = opaque;
+ PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path("/machine/q35", NULL),
+ TYPE_PCI_HOST_BRIDGE);
+ if (!s->mig_enabled) {
+ pci_set_long(&dev->config[Q35_PCI_HOST_CONFIG_REG], s->config_reg);
+ }
return 0;
}
@@ -521,6 +550,7 @@ static const VMStateDescription vmstate_mch = {
.name = "mch",
.version_id = 1,
.minimum_version_id = 1,
+ .pre_save = mch_pre_save,
.post_load = mch_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),