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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:20:36 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions Date: Wed, 22 Jul 2020 17:16:05 +0800 Message-Id: <20200722091641.8834-43-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 ++++ target/riscv/insn_trans/trans_rvv.inc.c | 27 +++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4be1b88e2d..0e1d6b3ead 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -595,6 +595,10 @@ vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 56cd7444f2..85f22a1495 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3527,3 +3527,30 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) } return false; } + +/* + * Whole Vector Register Move Instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 17.6) + */ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + ((a->rd & ((LEN) - 1)) == 0) && \ + ((a->rs2 & ((LEN) - 1)) == 0)) { \ + for (int i = 0; i < LEN; ++i) { \ + /* EEW = 8 */ \ + tcg_gen_gvec_mov(8, vreg_ofs(s, a->rd + i), \ + vreg_ofs(s, a->rs2 + i), \ + s->vlen / 8, s->vlen / 8); \ + } \ + mark_vs_dirty(s); \ + return true; \ + } \ + return false; \ +} + +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)