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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id 138sm637932wmb.1.2020.07.20.11.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 11:26:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH-not-for-5.1?] hw/isa/isa-bus: Ensure ISA I/O regions are 8/16/32-bit accessible Date: Mon, 20 Jul 2020 20:26:13 +0200 Message-Id: <20200720182613.10857-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , Michael Tokarev , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since commit 5d971f9e67 we don't accept mismatching sizes in memory_region_access_valid(). This gives troubles when a device is on an ISA bus, because the CPU is free to use 8/16/32-bit accesses on the bus, regardless what range is valid for the device. Add a check to ensure devices plugged on the ISA bus can accept 8/16/32-bits accesses. Related bug reports: - https://lore.kernel.org/xen-devel/20200630170913.123646-1-anthony.perard@citrix.com/T/ - https://bugs.debian.org/964793 - https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=964247 - https://bugs.launchpad.net/bugs/1886318 Signed-off-by: Philippe Mathieu-Daudé --- MST: I really don't like this approach, I think the ISA bus should adjust the access. --- hw/isa/isa-bus.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c index 58fde178f9..3d97ad1bdd 100644 --- a/hw/isa/isa-bus.c +++ b/hw/isa/isa-bus.c @@ -132,6 +132,17 @@ static inline void isa_init_ioport(ISADevice *dev, uint16_t ioport) void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start) { + if (io->ops->valid.min_access_size > 1) { + /* CPU can always use 8-bit accesses on an ISA bus */ + error_report("ISA device '%s' requires I/O min_access_size of 1", + object_get_typename(OBJECT(dev))); + exit(1); + } else if (io->ops->valid.max_access_size < 4) { + /* CPU can always use 32-bit accesses on an ISA bus */ + error_report("ISA device '%s' requires I/O max_access_size of 4", + object_get_typename(OBJECT(dev))); + exit(1); + } memory_region_add_subregion(isabus->address_space_io, start, io); isa_init_ioport(dev, start); }