From patchwork Sat Jul 11 16:16:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1327348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B3wBt6N3Tz9sRW for ; Sun, 12 Jul 2020 02:21:09 +1000 (AEST) Received: from localhost ([::1]:33424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIFP-0002JU-Fp for incoming@patchwork.ozlabs.org; Sat, 11 Jul 2020 12:21:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDI-0007FZ-TM; Sat, 11 Jul 2020 12:18:56 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:57681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001Lw-Tt; Sat, 11 Jul 2020 12:18:56 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.669281-0.0017065-0.329012; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03301; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:39 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 03/11] riscv: Add RV64A instructions description Date: Sun, 12 Jul 2020 00:16:47 +0800 Message-Id: <20200711161655.2856-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Ensure $rs2 != $rs1, so that the $rs2 register's value will not be covered when setting the $rs1 register's value to get a valid address. Signed-off-by: LIU Zhiwei --- rv64.risu | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/rv64.risu b/rv64.risu index 2c4154e..ad5dee9 100644 --- a/rv64.risu +++ b/rv64.risu @@ -180,3 +180,93 @@ REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \ REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \ !constraints { greg($rd) && greg($rs1) && greg($rs2); } + +@RV64A + +LR_W RISCV 00010 imm:2 00000 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(4); reg($rs1, $rd); } + +SC_W RISCV 00011 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOSWAP_W RISCV 00001 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOADD_W RISCV 00000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOXOR_W RISCV 00100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOAND_W RISCV 01100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOOR_W RISCV 01000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMIN_W RISCV 10000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMAX_W RISCV 10100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMINU_W RISCV 11000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMAXU_W RISCV 11100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +LR_D RISCV 00010 imm:2 00000 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(8); reg($rs1, $rd); } + +SC_D RISCV 00011 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOSWAP_D RISCV 00001 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOADD_D RISCV 00000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOXOR_D RISCV 00100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOAND_D RISCV 01100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOOR_D RISCV 01000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMIN_D RISCV 10000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMAX_D RISCV 10100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMINU_D RISCV 11000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMAXU_D RISCV 11100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); }