Message ID | 20200707154336.4963-1-lazyparser@gmail.com |
---|---|
State | New |
Headers | show |
Series | disas/riscv: Fix incorrect disassembly for `imm20` operand. | expand |
On 7/7/20 8:43 AM, Wei Wu wrote: > static int32_t operand_imm20(rv_inst inst) > { > - return (((int64_t)inst << 32) >> 44) << 12; > + return ((int64_t)inst << 32) >> 44; > } There's no point in casting to int64_t, for one. But it would be better to use sextract32(inst, 12, 20). r~
diff --git a/disas/riscv.c b/disas/riscv.c index 278d9be924..a2b6472bd8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst) static int32_t operand_imm20(rv_inst inst) { - return (((int64_t)inst << 32) >> 44) << 12; + return ((int64_t)inst << 32) >> 44; } static int32_t operand_jimm20(rv_inst inst)
`imm20` operand type is used in LUI/AUIPC and other instructions. The value should not be left shifted 12bits for disassembly output. Signed-off-by: Wei Wu <lazyparser@gmail.com> --- disas/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)