[PULL,v2,03/64] hw/riscv: Allow 64 bit access to SiFive CLINT

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org,
	qemu-devel@nongnu.org
Subject: [PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT
Date: Thu,  2 Jul 2020 09:22:53 -0700
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Message ID	20200702162354.928528-4-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: oGYTJ7UemHNF5lBZg+rU5k8g+IswRE88ZEs/yZl+2lR7Gy/F4c0DGIXZp+UzbCd383boGPwG2S NM/nig4JSdNx8Wr9wZ0mcdhl195vdHCYrR4YqyPCnQtBSMjcVdK2CV/L30crvBsLM+tQButwcC kMW0IGxuRfTlpJRtQWem/rIn86bTXDjXEcYRQWRZv1OFTSCNlI1YLFTqO+JyEVRaN8Hc2ORoxp AUDY6DxXDfrRkpoRHD8nU8FZymy0Y70R7snOACCCNsFv876WpRtpuKeGsi2wbSIWjywA3n5n2L 14A= IronPort-SDR: 6O0He1zUgHEun4hTFDsnyPjvPg6iIiP1IdIHMUOp39qlxo0AE163oYHSaMnm2lf67Ar2L0nNDg HrJqzqj0DapmJMtp2Fz79gjcelgCkyW+E= IronPort-SDR: +BtPlX/Lvl35HspGrH+u6gie+KDDcbsSigaVvfddsNkDBgXuO3cAFqVXPkmSu7vDw7gGwOffWp o+fyErEQ2ilg== WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT Date: Thu, 2 Jul 2020 09:22:53 -0700 Message-Id: <20200702162354.928528-4-alistair.francis@wdc.com> In-Reply-To: <20200702162354.928528-1-alistair.francis@wdc.com> References: <20200702162354.928528-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=4451fe355=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com Precedence: list Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,v2,01/64] riscv: plic: Honour source priorities \| expand [PULL,v2,01/64] riscv: plic: Honour source priorities [PULL,v2,02/64] riscv: plic: Add a couple of mising sifive_plic_update calls [PULL,v2,03/64] hw/riscv: Allow 64 bit access to SiFive CLINT [PULL,v2,04/64] target/riscv: add vector extension field in CPURISCVState [PULL,v2,05/64] target/riscv: implementation-defined constant parameters [PULL,v2,06/64] target/riscv: support vector extension csr [PULL,v2,07/64] target/riscv: add vector configure instruction [PULL,v2,08/64] target/riscv: add an internals.h header [PULL,v2,09/64] target/riscv: add vector stride load and store instructions [PULL,v2,10/64] target/riscv: add vector index load and store instructions [PULL,v2,11/64] target/riscv: add fault-only-first unit stride load [PULL,v2,12/64] target/riscv: add vector amo operations [PULL,v2,13/64] target/riscv: vector single-width integer add and subtract [PULL,v2,14/64] target/riscv: vector widening integer add and subtract [PULL,v2,15/64] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions [PULL,v2,16/64] target/riscv: vector bitwise logical instructions [PULL,v2,17/64] target/riscv: vector single-width bit shift instructions [PULL,v2,18/64] target/riscv: vector narrowing integer right shift instructions [PULL,v2,19/64] target/riscv: vector integer comparison instructions [PULL,v2,20/64] target/riscv: vector integer min/max instructions [PULL,v2,21/64] target/riscv: vector single-width integer multiply instructions [PULL,v2,22/64] target/riscv: vector integer divide instructions [PULL,v2,23/64] target/riscv: vector widening integer multiply instructions [PULL,v2,24/64] target/riscv: vector single-width integer multiply-add instructions [PULL,v2,25/64] target/riscv: vector widening integer multiply-add instructions [PULL,v2,26/64] target/riscv: vector integer merge and move instructions [PULL,v2,27/64] target/riscv: vector single-width saturating add and subtract [PULL,v2,28/64] target/riscv: vector single-width averaging add and subtract [PULL,v2,29/64] target/riscv: vector single-width fractional multiply with rounding and saturation [PULL,v2,30/64] target/riscv: vector widening saturating scaled multiply-add [PULL,v2,31/64] target/riscv: vector single-width scaling shift instructions [PULL,v2,32/64] target/riscv: vector narrowing fixed-point clip instructions [PULL,v2,33/64] target/riscv: vector single-width floating-point add/subtract instructions [PULL,v2,34/64] target/riscv: vector widening floating-point add/subtract instructions [PULL,v2,35/64] target/riscv: vector single-width floating-point multiply/divide instructions [PULL,v2,36/64] target/riscv: vector widening floating-point multiply [PULL,v2,37/64] target/riscv: vector single-width floating-point fused multiply-add instructions [PULL,v2,38/64] target/riscv: vector widening floating-point fused multiply-add instructions [PULL,v2,39/64] target/riscv: vector floating-point square-root instruction [PULL,v2,40/64] target/riscv: vector floating-point min/max instructions [PULL,v2,41/64] target/riscv: vector floating-point sign-injection instructions [PULL,v2,42/64] target/riscv: vector floating-point compare instructions [PULL,v2,43/64] target/riscv: vector floating-point classify instructions [PULL,v2,44/64] target/riscv: vector floating-point merge instructions [PULL,v2,45/64] target/riscv: vector floating-point/integer type-convert instructions [PULL,v2,46/64] target/riscv: widening floating-point/integer type-convert instructions [PULL,v2,47/64] target/riscv: narrowing floating-point/integer type-convert instructions [PULL,v2,48/64] target/riscv: vector single-width integer reduction instructions [PULL,v2,49/64] target/riscv: vector wideing integer reduction instructions [PULL,v2,50/64] target/riscv: vector single-width floating-point reduction instructions [PULL,v2,51/64] target/riscv: vector widening floating-point reduction instructions [PULL,v2,52/64] target/riscv: vector mask-register logical instructions [PULL,v2,53/64] target/riscv: vector mask population count vmpopc [PULL,v2,54/64] target/riscv: vmfirst find-first-set mask bit [PULL,v2,55/64] target/riscv: set-X-first mask bit [PULL,v2,56/64] target/riscv: vector iota instruction [PULL,v2,57/64] target/riscv: vector element index instruction [PULL,v2,58/64] target/riscv: integer extract instruction [PULL,v2,59/64] target/riscv: integer scalar move instruction [PULL,v2,60/64] target/riscv: floating-point scalar move instructions [PULL,v2,61/64] target/riscv: vector slide instructions [PULL,v2,62/64] target/riscv: vector register gather instruction [PULL,v2,63/64] target/riscv: vector compress instruction [PULL,v2,64/64] target/riscv: configure and turn on vector extension from command line

[PULL,v2,03/64] hw/riscv: Allow 64 bit access to SiFive CLINT

Commit Message

Patch