[PULL,07/63] target/riscv: add an internals.h header

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org,
	qemu-devel@nongnu.org
Subject: [PULL 07/63] target/riscv: add an internals.h header
Date: Fri, 26 Jun 2020 14:43:14 -0700
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Message ID	20200626214410.3613258-8-alistair.francis@wdc.com
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Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: 7cmxd1F1AnCP+kPxrbeVZK2MmKoVlc5JIakBRBJMDQc+QvpTLG5e18JKD9srqVAx/j38wcHy7s +a6VHhuvZf3+ELJ9cNzfI/+wxOr8gockJd60dg2EvAPq0TErZ0yukyAeiegeMKWY5Gfw71W76w H+3NRssVqrvbt2UFMnW5SfBVdvaLtnLwu4I+/tqNFurfaS6H4yxdhoiLeWoXLclDN9XoWNTAhF ENuUepvgcnXdOICAcdS4bb141AP4JIH94XUzRfAWuhe+hzZJ6lAFI2g+RJL/h3GSp2A/ltDFtF SzM= IronPort-SDR: 9QUk9J+kEeUHmy+jJr1FvaOH+h6isNfQ+uF/Yx9FC7mnHINdswdjZfawj4jAsygTHThHhgll7u RHskC1wFyMw2TuAoTCMhD8kwssE0dTJMs= IronPort-SDR: oa+/cNjfBJpNqK+RCAKjGsdC/rpma+EOwI49mUvEgLQneKNRrWsNbiBzbHvAPe8kMunl6X5d+x B9U6soAzk7RA== WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 07/63] target/riscv: add an internals.h header Date: Fri, 26 Jun 2020 14:43:14 -0700 Message-Id: <20200626214410.3613258-8-alistair.francis@wdc.com> In-Reply-To: <20200626214410.3613258-1-alistair.francis@wdc.com> References: <20200626214410.3613258-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=439617756=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com Precedence: list Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/63] riscv: plic: Honour source priorities \| expand [PULL,01/63] riscv: plic: Honour source priorities [PULL,02/63] riscv: plic: Add a couple of mising sifive_plic_update calls [PULL,03/63] target/riscv: add vector extension field in CPURISCVState [PULL,04/63] target/riscv: implementation-defined constant parameters [PULL,05/63] target/riscv: support vector extension csr [PULL,06/63] target/riscv: add vector configure instruction [PULL,07/63] target/riscv: add an internals.h header [PULL,08/63] target/riscv: add vector stride load and store instructions [PULL,09/63] target/riscv: add vector index load and store instructions [PULL,10/63] target/riscv: add fault-only-first unit stride load [PULL,11/63] target/riscv: add vector amo operations [PULL,12/63] target/riscv: vector single-width integer add and subtract [PULL,13/63] target/riscv: vector widening integer add and subtract [PULL,14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions [PULL,15/63] target/riscv: vector bitwise logical instructions [PULL,16/63] target/riscv: vector single-width bit shift instructions [PULL,17/63] target/riscv: vector narrowing integer right shift instructions [PULL,18/63] target/riscv: vector integer comparison instructions [PULL,19/63] target/riscv: vector integer min/max instructions [PULL,20/63] target/riscv: vector single-width integer multiply instructions [PULL,21/63] target/riscv: vector integer divide instructions [PULL,22/63] target/riscv: vector widening integer multiply instructions [PULL,23/63] target/riscv: vector single-width integer multiply-add instructions [PULL,24/63] target/riscv: vector widening integer multiply-add instructions [PULL,25/63] target/riscv: vector integer merge and move instructions [PULL,26/63] target/riscv: vector single-width saturating add and subtract [PULL,27/63] target/riscv: vector single-width averaging add and subtract [PULL,28/63] target/riscv: vector single-width fractional multiply with rounding and saturation [PULL,29/63] target/riscv: vector widening saturating scaled multiply-add [PULL,30/63] target/riscv: vector single-width scaling shift instructions [PULL,31/63] target/riscv: vector narrowing fixed-point clip instructions [PULL,32/63] target/riscv: vector single-width floating-point add/subtract instructions [PULL,33/63] target/riscv: vector widening floating-point add/subtract instructions [PULL,34/63] target/riscv: vector single-width floating-point multiply/divide instructions [PULL,35/63] target/riscv: vector widening floating-point multiply [PULL,36/63] target/riscv: vector single-width floating-point fused multiply-add instructions [PULL,37/63] target/riscv: vector widening floating-point fused multiply-add instructions [PULL,38/63] target/riscv: vector floating-point square-root instruction [PULL,39/63] target/riscv: vector floating-point min/max instructions [PULL,40/63] target/riscv: vector floating-point sign-injection instructions [PULL,41/63] target/riscv: vector floating-point compare instructions [PULL,42/63] target/riscv: vector floating-point classify instructions [PULL,43/63] target/riscv: vector floating-point merge instructions [PULL,44/63] target/riscv: vector floating-point/integer type-convert instructions [PULL,45/63] target/riscv: widening floating-point/integer type-convert instructions [PULL,46/63] target/riscv: narrowing floating-point/integer type-convert instructions [PULL,47/63] target/riscv: vector single-width integer reduction instructions [PULL,48/63] target/riscv: vector wideing integer reduction instructions [PULL,49/63] target/riscv: vector single-width floating-point reduction instructions [PULL,50/63] target/riscv: vector widening floating-point reduction instructions [PULL,51/63] target/riscv: vector mask-register logical instructions [PULL,52/63] target/riscv: vector mask population count vmpopc [PULL,53/63] target/riscv: vmfirst find-first-set mask bit [PULL,54/63] target/riscv: set-X-first mask bit [PULL,55/63] target/riscv: vector iota instruction [PULL,56/63] target/riscv: vector element index instruction [PULL,57/63] target/riscv: integer extract instruction [PULL,58/63] target/riscv: integer scalar move instruction [PULL,59/63] target/riscv: floating-point scalar move instructions [PULL,60/63] target/riscv: vector slide instructions [PULL,61/63] target/riscv: vector register gather instruction [PULL,62/63] target/riscv: vector compress instruction [PULL,63/63] target/riscv: configure and turn on vector extension from command line

[PULL,07/63] target/riscv: add an internals.h header

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