| Message ID | 20200530092204.1746-1-fangying1@huawei.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm/cpu: adjust virtual time for cortex series cpu | expand |
On Sat, 30 May 2020 at 10:22, Ying Fang <fangying1@huawei.com> wrote: > > Virtual time adjustment was implemented for virt-5.0 machine type, > but the cpu property was enabled only for host-passthrough and > max cpu model. Let's add it for arm cortex series cpu which has > the gernic timer feature enabled. > > Signed-off-by: Ying Fang <fangying1@huawei.com> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 32bec156f2..a564141b22 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1973,6 +1973,9 @@ static void cortex_a7_initfn(Object *obj) > cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ > cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ > define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ > + if (kvm_enabled()) { > + kvm_arm_add_vcpu_properties(obj); > + } > } If we have the same bit of code in all these initfns, that suggests we should probably actually be doing this in some more generic place conditional on some cpu feature or other test. The commit message suggests we should add this property for every CPU which is using KVM and has the generic timers, in which case we could perhaps have the call to kvm_arm_add_vcpu_properties moved to arm_cpu_post_init(), and then have the kvm_arm_add_vcpu_properties function check the ARM_FEATURE_GENERIC_TIMER flag to see whether to add the property or not. thanks -- PMM
On 2020/6/1 20:41, Peter Maydell wrote: > On Sat, 30 May 2020 at 10:22, Ying Fang <fangying1@huawei.com> wrote: >> >> Virtual time adjustment was implemented for virt-5.0 machine type, >> but the cpu property was enabled only for host-passthrough and >> max cpu model. Let's add it for arm cortex series cpu which has >> the gernic timer feature enabled. >> >> Signed-off-by: Ying Fang <fangying1@huawei.com> >> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >> index 32bec156f2..a564141b22 100644 >> --- a/target/arm/cpu.c >> +++ b/target/arm/cpu.c >> @@ -1973,6 +1973,9 @@ static void cortex_a7_initfn(Object *obj) >> cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ >> cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ >> define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ >> + if (kvm_enabled()) { >> + kvm_arm_add_vcpu_properties(obj); >> + } >> } > > If we have the same bit of code in all these initfns, > that suggests we should probably actually be doing this > in some more generic place conditional on some cpu feature > or other test. The commit message suggests we should add > this property for every CPU which is using KVM and has > the generic timers, in which case we could perhaps > have the call to kvm_arm_add_vcpu_properties moved to > arm_cpu_post_init(), and then have the kvm_arm_add_vcpu_properties > function check the ARM_FEATURE_GENERIC_TIMER flag to see > whether to add the property or not. Thanks for pointing it out, to put kvm_arm_add_vcpu_properties into arm_cpu_post_init is much better. I will send a V2. > > thanks > -- PMM > > . > Thanks Ying.
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 32bec156f2..a564141b22 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1973,6 +1973,9 @@ static void cortex_a7_initfn(Object *obj) cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ + if (kvm_enabled()) { + kvm_arm_add_vcpu_properties(obj); + } } static void cortex_a15_initfn(Object *obj) @@ -2015,6 +2018,9 @@ static void cortex_a15_initfn(Object *obj) cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ define_arm_cp_regs(cpu, cortexa15_cp_reginfo); + if (kvm_enabled()) { + kvm_arm_add_vcpu_properties(obj); + } } #ifndef TARGET_AARCH64 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cbc5c3868f..3922347b83 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -137,6 +137,9 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + if (kvm_enabled()) { + kvm_arm_add_vcpu_properties(obj); + } } static void aarch64_a53_initfn(Object *obj) @@ -190,6 +193,9 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + if (kvm_enabled()) { + kvm_arm_add_vcpu_properties(obj); + } } static void aarch64_a72_initfn(Object *obj) @@ -241,6 +247,9 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + if (kvm_enabled()) { + kvm_arm_add_vcpu_properties(obj); + } } void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
Virtual time adjustment was implemented for virt-5.0 machine type, but the cpu property was enabled only for host-passthrough and max cpu model. Let's add it for arm cortex series cpu which has the gernic timer feature enabled. Signed-off-by: Ying Fang <fangying1@huawei.com>