| Message ID | 20200521192133.127559-7-hskinnemoen@google.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines | expand |
On Thu, 21 May 2020 at 20:39, Havard Skinnemoen <hskinnemoen@google.com> wrote: > > This adds two new machines: > > - npcm750-evb: Nuvoton NPCM750 Evaluation Board. > - quanta-gsj: A board with a NPCM730 chip. You could note that these are the two boards supported by OpenBMC. > They rely on the NPCM7xx SoC device to do the heavy lifting. They are > almost completely identical at the moment, apart from the SoC type, > which currently only changes the reset contents of one register > (GCR.MDLR), but they might grow apart a bit more as more functionality > is added. > > Both machines can boot the Linux kernel into /bin/sh. > > Reviewed-by: Tyrone Ting <kfting@nuvoton.com> > Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
On 5/21/20 9:21 PM, Havard Skinnemoen wrote: > This adds two new machines: > > - npcm750-evb: Nuvoton NPCM750 Evaluation Board. > - quanta-gsj: A board with a NPCM730 chip. > > They rely on the NPCM7xx SoC device to do the heavy lifting. They are > almost completely identical at the moment, apart from the SoC type, > which currently only changes the reset contents of one register > (GCR.MDLR), but they might grow apart a bit more as more functionality > is added. > > Both machines can boot the Linux kernel into /bin/sh. > > Reviewed-by: Tyrone Ting <kfting@nuvoton.com> > Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > hw/arm/Makefile.objs | 2 +- > hw/arm/npcm7xx_boards.c | 108 +++++++++++++++++++++++++++++++++++++++ > include/hw/arm/npcm7xx.h | 19 +++++++ > 3 files changed, 128 insertions(+), 1 deletion(-) > create mode 100644 hw/arm/npcm7xx_boards.c > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > index 13d163a599..c333548ce1 100644 > --- a/hw/arm/Makefile.objs > +++ b/hw/arm/Makefile.objs > @@ -41,7 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o > obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o > obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o > obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o > -obj-$(CONFIG_NPCM7XX) += npcm7xx.o > +obj-$(CONFIG_NPCM7XX) += npcm7xx.o npcm7xx_boards.o > obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o > obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o > diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c > new file mode 100644 > index 0000000000..b89819f6e2 > --- /dev/null > +++ b/hw/arm/npcm7xx_boards.c > @@ -0,0 +1,108 @@ > +/* > + * Machine definitions for boards featuring an NPCM7xx SoC. > + * > + * Copyright 2020 Google LLC > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/arm/boot.h" > +#include "hw/arm/npcm7xx.h" > +#include "hw/core/cpu.h" > +#include "qapi/error.h" > +#include "qemu/units.h" > + > +static struct arm_boot_info npcm7xx_binfo = { > + .loader_start = NPCM7XX_LOADER_START, > + .smp_loader_start = NPCM7XX_SMP_LOADER_START, > + .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, > + .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, > + .write_secondary_boot = npcm7xx_write_secondary_boot, > + .board_id = -1, > +}; > + > +static void npcm7xx_machine_init(MachineState *machine) > +{ > + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); > + NPCM7xxState *soc; > + > + soc = NPCM7XX(object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", > + &error_abort, NULL)); > + object_property_set_int(OBJECT(soc), machine->smp.cpus, "num-cpus", > + &error_abort); > + object_property_set_link(OBJECT(soc), OBJECT(machine->ram), "dram", > + &error_abort); > + object_property_set_bool(OBJECT(soc), true, "realized", &error_abort); > + > + npcm7xx_binfo.ram_size = machine->ram_size; > + npcm7xx_binfo.nb_cpus = machine->smp.cpus; > + > + arm_load_kernel(soc->cpu[0], machine, &npcm7xx_binfo); > +} > + > +static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) > +{ > + MachineClass *mc = MACHINE_CLASS(oc); > + > + mc->init = npcm7xx_machine_init; > + mc->max_cpus = NPCM7XX_MAX_NUM_CPUS; > + mc->default_cpus = NPCM7XX_MAX_NUM_CPUS; > + mc->no_floppy = 1; > + mc->no_cdrom = 1; > + mc->no_parallel = 1; > + mc->default_ram_id = "ram"; > +} > + > +/* > + * Schematics: > + * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf > + */ > +static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) > +{ > + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); > + MachineClass *mc = MACHINE_CLASS(oc); > + > + mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)"; > + nmc->soc_type = TYPE_NPCM750; > + mc->default_ram_size = 512 * MiB; > +}; > + > +static void gsj_machine_class_init(ObjectClass *oc, void *data) > +{ > + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); > + MachineClass *mc = MACHINE_CLASS(oc); > + > + mc->desc = "Quanta GSJ (Cortex A9)"; > + nmc->soc_type = TYPE_NPCM730; > + mc->default_ram_size = 512 * MiB; > +}; > + > +static const TypeInfo npcm7xx_machine_types[] = { > + { > + .name = TYPE_NPCM7XX_MACHINE, > + .parent = TYPE_MACHINE, > + .instance_size = sizeof(NPCM7xxMachine), > + .class_size = sizeof(NPCM7xxMachineClass), > + .class_init = npcm7xx_machine_class_init, > + .abstract = true, > + }, { > + .name = MACHINE_TYPE_NAME("npcm750-evb"), > + .parent = TYPE_NPCM7XX_MACHINE, > + .class_init = npcm750_evb_machine_class_init, > + }, { > + .name = MACHINE_TYPE_NAME("quanta-gsj"), > + .parent = TYPE_NPCM7XX_MACHINE, > + .class_init = gsj_machine_class_init, > + }, > +}; > + > +DEFINE_TYPES(npcm7xx_machine_types) > diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h > index 0a8798dd24..c1a108e89a 100644 > --- a/include/hw/arm/npcm7xx.h > +++ b/include/hw/arm/npcm7xx.h > @@ -30,6 +30,25 @@ > #define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */ > #define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */ > > +typedef struct NPCM7xxMachine { > + MachineState parent; > +} NPCM7xxMachine; > + > +#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") > +#define NPCM7XX_MACHINE(obj) \ > + OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) > + > +typedef struct NPCM7xxMachineClass { > + MachineClass parent; > + > + const char *soc_type; > +} NPCM7xxMachineClass; > + > +#define NPCM7XX_MACHINE_CLASS(klass) \ > + OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) > +#define NPCM7XX_MACHINE_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) > + > typedef struct NPCM7xxState { > DeviceState parent; > >
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 13d163a599..c333548ce1 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -41,7 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o -obj-$(CONFIG_NPCM7XX) += npcm7xx.o +obj-$(CONFIG_NPCM7XX) += npcm7xx.o npcm7xx_boards.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c new file mode 100644 index 0000000000..b89819f6e2 --- /dev/null +++ b/hw/arm/npcm7xx_boards.c @@ -0,0 +1,108 @@ +/* + * Machine definitions for boards featuring an NPCM7xx SoC. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/arm/boot.h" +#include "hw/arm/npcm7xx.h" +#include "hw/core/cpu.h" +#include "qapi/error.h" +#include "qemu/units.h" + +static struct arm_boot_info npcm7xx_binfo = { + .loader_start = NPCM7XX_LOADER_START, + .smp_loader_start = NPCM7XX_SMP_LOADER_START, + .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, + .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, + .write_secondary_boot = npcm7xx_write_secondary_boot, + .board_id = -1, +}; + +static void npcm7xx_machine_init(MachineState *machine) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); + NPCM7xxState *soc; + + soc = NPCM7XX(object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", + &error_abort, NULL)); + object_property_set_int(OBJECT(soc), machine->smp.cpus, "num-cpus", + &error_abort); + object_property_set_link(OBJECT(soc), OBJECT(machine->ram), "dram", + &error_abort); + object_property_set_bool(OBJECT(soc), true, "realized", &error_abort); + + npcm7xx_binfo.ram_size = machine->ram_size; + npcm7xx_binfo.nb_cpus = machine->smp.cpus; + + arm_load_kernel(soc->cpu[0], machine, &npcm7xx_binfo); +} + +static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->init = npcm7xx_machine_init; + mc->max_cpus = NPCM7XX_MAX_NUM_CPUS; + mc->default_cpus = NPCM7XX_MAX_NUM_CPUS; + mc->no_floppy = 1; + mc->no_cdrom = 1; + mc->no_parallel = 1; + mc->default_ram_id = "ram"; +} + +/* + * Schematics: + * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf + */ +static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)"; + nmc->soc_type = TYPE_NPCM750; + mc->default_ram_size = 512 * MiB; +}; + +static void gsj_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "Quanta GSJ (Cortex A9)"; + nmc->soc_type = TYPE_NPCM730; + mc->default_ram_size = 512 * MiB; +}; + +static const TypeInfo npcm7xx_machine_types[] = { + { + .name = TYPE_NPCM7XX_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(NPCM7xxMachine), + .class_size = sizeof(NPCM7xxMachineClass), + .class_init = npcm7xx_machine_class_init, + .abstract = true, + }, { + .name = MACHINE_TYPE_NAME("npcm750-evb"), + .parent = TYPE_NPCM7XX_MACHINE, + .class_init = npcm750_evb_machine_class_init, + }, { + .name = MACHINE_TYPE_NAME("quanta-gsj"), + .parent = TYPE_NPCM7XX_MACHINE, + .class_init = gsj_machine_class_init, + }, +}; + +DEFINE_TYPES(npcm7xx_machine_types) diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 0a8798dd24..c1a108e89a 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -30,6 +30,25 @@ #define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */ #define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */ +typedef struct NPCM7xxMachine { + MachineState parent; +} NPCM7xxMachine; + +#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") +#define NPCM7XX_MACHINE(obj) \ + OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) + +typedef struct NPCM7xxMachineClass { + MachineClass parent; + + const char *soc_type; +} NPCM7xxMachineClass; + +#define NPCM7XX_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) +#define NPCM7XX_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) + typedef struct NPCM7xxState { DeviceState parent;