| Message ID | 20200521094413.10425-42-zhiwei_liu@c-sky.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: support vector extension v0.7.1 | expand |
On Thu, May 21, 2020 at 4:07 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/fpu_helper.c | 33 +-------- > target/riscv/helper.h | 4 ++ > target/riscv/insn32.decode | 1 + > target/riscv/insn_trans/trans_rvv.inc.c | 3 + > target/riscv/internals.h | 5 ++ > target/riscv/vector_helper.c | 91 +++++++++++++++++++++++++ > 6 files changed, 107 insertions(+), 30 deletions(-) > > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 262610e837..fdbdffaef2 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -22,6 +22,7 @@ > #include "exec/exec-all.h" > #include "exec/helper-proto.h" > #include "fpu/softfloat.h" > +#include "internals.h" > > target_ulong riscv_cpu_get_fflags(CPURISCVState *env) > { > @@ -239,21 +240,7 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) > > target_ulong helper_fclass_s(uint64_t frs1) > { > - float32 f = frs1; > - bool sign = float32_is_neg(f); > - > - if (float32_is_infinity(f)) { > - return sign ? 1 << 0 : 1 << 7; > - } else if (float32_is_zero(f)) { > - return sign ? 1 << 3 : 1 << 4; > - } else if (float32_is_zero_or_denormal(f)) { > - return sign ? 1 << 2 : 1 << 5; > - } else if (float32_is_any_nan(f)) { > - float_status s = { }; /* for snan_bit_is_one */ > - return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; > - } else { > - return sign ? 1 << 1 : 1 << 6; > - } > + return fclass_s(frs1); > } > > uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) > @@ -362,19 +349,5 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1) > > target_ulong helper_fclass_d(uint64_t frs1) > { > - float64 f = frs1; > - bool sign = float64_is_neg(f); > - > - if (float64_is_infinity(f)) { > - return sign ? 1 << 0 : 1 << 7; > - } else if (float64_is_zero(f)) { > - return sign ? 1 << 3 : 1 << 4; > - } else if (float64_is_zero_or_denormal(f)) { > - return sign ? 1 << 2 : 1 << 5; > - } else if (float64_is_any_nan(f)) { > - float_status s = { }; /* for snan_bit_is_one */ > - return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; > - } else { > - return sign ? 1 << 1 : 1 << 6; > - } > + return fclass_d(frs1); > } > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index bedd4d0114..23b268df90 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -990,3 +990,7 @@ DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) > DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) > DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) > + > +DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) > +DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) > +DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index b0f1c54d53..23e80fe954 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -512,6 +512,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm > vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm > vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm > vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm > +vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index 4a45c00ffb..621220e5ff 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -2174,3 +2174,6 @@ GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) > GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) > GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) > GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) > + > +/* Vector Floating-Point Classify Instruction */ > +GEN_OPFV_TRANS(vfclass_v, opfv_check) > diff --git a/target/riscv/internals.h b/target/riscv/internals.h > index 52f6af2513..ed2ad7f0f1 100644 > --- a/target/riscv/internals.h > +++ b/target/riscv/internals.h > @@ -30,4 +30,9 @@ FIELD(VDATA, WD, 11, 1) > > /* set float rounding mode */ > bool riscv_cpu_set_rounding_mode(CPURISCVState *env, uint32_t rm); > + > +/* float point classify helpers */ > +target_ulong fclass_h(uint64_t frs1); > +target_ulong fclass_s(uint64_t frs1); > +target_ulong fclass_d(uint64_t frs1); > #endif > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 92227228b7..63d8873c0a 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4102,3 +4102,94 @@ GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) > GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) > GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) > GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) > + > +/* Vector Floating-Point Classify Instruction */ > +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ > +static void do_##NAME(void *vd, void *vs2, int i) \ > +{ \ > + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ > + *((TD *)vd + HD(i)) = OP(s2); \ > +} > + > +#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \ > +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ > + CPURISCVState *env, uint32_t desc) \ > +{ \ > + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ > + uint32_t mlen = vext_mlen(desc); \ > + uint32_t vm = vext_vm(desc); \ > + uint32_t vl = env->vl; \ > + uint32_t i; \ > + \ > + for (i = 0; i < vl; i++) { \ > + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ > + continue; \ > + } \ > + do_##NAME(vd, vs2, i); \ > + } \ > + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ > +} > + > +target_ulong fclass_h(uint64_t frs1) > +{ > + float16 f = frs1; > + bool sign = float16_is_neg(f); > + > + if (float16_is_infinity(f)) { > + return sign ? 1 << 0 : 1 << 7; > + } else if (float16_is_zero(f)) { > + return sign ? 1 << 3 : 1 << 4; > + } else if (float16_is_zero_or_denormal(f)) { > + return sign ? 1 << 2 : 1 << 5; > + } else if (float16_is_any_nan(f)) { > + float_status s = { }; /* for snan_bit_is_one */ > + return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; > + } else { > + return sign ? 1 << 1 : 1 << 6; > + } > +} > + > +target_ulong fclass_s(uint64_t frs1) > +{ > + float32 f = frs1; > + bool sign = float32_is_neg(f); > + > + if (float32_is_infinity(f)) { > + return sign ? 1 << 0 : 1 << 7; > + } else if (float32_is_zero(f)) { > + return sign ? 1 << 3 : 1 << 4; > + } else if (float32_is_zero_or_denormal(f)) { > + return sign ? 1 << 2 : 1 << 5; > + } else if (float32_is_any_nan(f)) { > + float_status s = { }; /* for snan_bit_is_one */ > + return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; > + } else { > + return sign ? 1 << 1 : 1 << 6; > + } > +} > + > +target_ulong fclass_d(uint64_t frs1) > +{ > + float64 f = frs1; > + bool sign = float64_is_neg(f); > + > + if (float64_is_infinity(f)) { > + return sign ? 1 << 0 : 1 << 7; > + } else if (float64_is_zero(f)) { > + return sign ? 1 << 3 : 1 << 4; > + } else if (float64_is_zero_or_denormal(f)) { > + return sign ? 1 << 2 : 1 << 5; > + } else if (float64_is_any_nan(f)) { > + float_status s = { }; /* for snan_bit_is_one */ > + return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; > + } else { > + return sign ? 1 << 1 : 1 << 6; > + } > +} > + > +RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h) > +RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s) > +RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) > +GEN_VEXT_V(vfclass_v_h, 2, 2, clearh) > +GEN_VEXT_V(vfclass_v_w, 4, 4, clearl) > +GEN_VEXT_V(vfclass_v_d, 8, 8, clearq) > -- > 2.23.0 > >
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 262610e837..fdbdffaef2 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "internals.h" target_ulong riscv_cpu_get_fflags(CPURISCVState *env) { @@ -239,21 +240,7 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) target_ulong helper_fclass_s(uint64_t frs1) { - float32 f = frs1; - bool sign = float32_is_neg(f); - - if (float32_is_infinity(f)) { - return sign ? 1 << 0 : 1 << 7; - } else if (float32_is_zero(f)) { - return sign ? 1 << 3 : 1 << 4; - } else if (float32_is_zero_or_denormal(f)) { - return sign ? 1 << 2 : 1 << 5; - } else if (float32_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; - } else { - return sign ? 1 << 1 : 1 << 6; - } + return fclass_s(frs1); } uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) @@ -362,19 +349,5 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1) target_ulong helper_fclass_d(uint64_t frs1) { - float64 f = frs1; - bool sign = float64_is_neg(f); - - if (float64_is_infinity(f)) { - return sign ? 1 << 0 : 1 << 7; - } else if (float64_is_zero(f)) { - return sign ? 1 << 3 : 1 << 4; - } else if (float64_is_zero_or_denormal(f)) { - return sign ? 1 << 2 : 1 << 5; - } else if (float64_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; - } else { - return sign ? 1 << 1 : 1 << 6; - } + return fclass_d(frs1); } diff --git a/target/riscv/helper.h b/target/riscv/helper.h index bedd4d0114..23b268df90 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -990,3 +990,7 @@ DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b0f1c54d53..23e80fe954 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -512,6 +512,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm +vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 4a45c00ffb..621220e5ff 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2174,3 +2174,6 @@ GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) + +/* Vector Floating-Point Classify Instruction */ +GEN_OPFV_TRANS(vfclass_v, opfv_check) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 52f6af2513..ed2ad7f0f1 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -30,4 +30,9 @@ FIELD(VDATA, WD, 11, 1) /* set float rounding mode */ bool riscv_cpu_set_rounding_mode(CPURISCVState *env, uint32_t rm); + +/* float point classify helpers */ +target_ulong fclass_h(uint64_t frs1); +target_ulong fclass_s(uint64_t frs1); +target_ulong fclass_d(uint64_t frs1); #endif diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 92227228b7..63d8873c0a 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4102,3 +4102,94 @@ GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) + +/* Vector Floating-Point Classify Instruction */ +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +target_ulong fclass_h(uint64_t frs1) +{ + float16 f = frs1; + bool sign = float16_is_neg(f); + + if (float16_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float16_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float16_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float16_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +target_ulong fclass_s(uint64_t frs1) +{ + float32 f = frs1; + bool sign = float32_is_neg(f); + + if (float32_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float32_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float32_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float32_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +target_ulong fclass_d(uint64_t frs1) +{ + float64 f = frs1; + bool sign = float64_is_neg(f); + + if (float64_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float64_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float64_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float64_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h) +RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s) +RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) +GEN_VEXT_V(vfclass_v_h, 2, 2, clearh) +GEN_VEXT_V(vfclass_v_w, 4, 4, clearl) +GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)