diff mbox series

[RFC,6/8] riscv: Add configure script

Message ID 20200430072139.4602-7-zhiwei_liu@c-sky.com
State New
Headers show
Series RISCV risu porting | expand

Commit Message

LIU Zhiwei April 30, 2020, 7:21 a.m. UTC
For RV64 risu, make CFLAGS="-march=rv64g"

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 configure | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Richard Henderson May 11, 2020, 6:06 p.m. UTC | #1
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +++ b/configure
> @@ -58,6 +58,8 @@ guess_arch() {
>          ARCH="m68k"
>      elif check_define __powerpc64__ ; then
>          ARCH="ppc64"
> +    elif check_define __riscv ; then
> +        ARCH="riscv64"
>      else
>          echo "This cpu is not supported by risu. Try -h. " >&2
>          exit 1

Why "riscv64" and not "riscv"?

You can't really say more without checking __riscv_xlen.


r~
LIU Zhiwei May 20, 2020, 1:45 a.m. UTC | #2
On 2020/5/12 2:06, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +++ b/configure
>> @@ -58,6 +58,8 @@ guess_arch() {
>>           ARCH="m68k"
>>       elif check_define __powerpc64__ ; then
>>           ARCH="ppc64"
>> +    elif check_define __riscv ; then
>> +        ARCH="riscv64"
>>       else
>>           echo "This cpu is not supported by risu. Try -h. " >&2
>>           exit 1
> Why "riscv64" and not "riscv"?
>
> You can't really say more without checking __riscv_xlen.
Thanks for point it out. I will add support for RV32 next patch set.

Zhiwei
>
> r~
LIU Zhiwei May 20, 2020, 2:28 a.m. UTC | #3
On 2020/5/20 9:45, LIU Zhiwei wrote:
>
> On 2020/5/12 2:06, Richard Henderson wrote:
>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>> +++ b/configure
>>> @@ -58,6 +58,8 @@ guess_arch() {
>>>           ARCH="m68k"
>>>       elif check_define __powerpc64__ ; then
>>>           ARCH="ppc64"
>>> +    elif check_define __riscv ; then
>>> +        ARCH="riscv64"
>>>       else
>>>           echo "This cpu is not supported by risu. Try -h. " >&2
>>>           exit 1
>> Why "riscv64" and not "riscv"?
>>
>> You can't really say more without checking __riscv_xlen.
> Thanks for point it out. I will add support for RV32 next patch set.
Perhaps not to support RV32, because I don't have hardware in RV32 to 
support Linux.

So the next patch set will focus on the rv64gc, and add more check for 
__riscv_xlen and __riscv_flen.

Zhiwei
>
>
> Zhiwei
>>
>> r~
>
diff mbox series

Patch

diff --git a/configure b/configure
index ca2d7db..5c9e967 100755
--- a/configure
+++ b/configure
@@ -58,6 +58,8 @@  guess_arch() {
         ARCH="m68k"
     elif check_define __powerpc64__ ; then
         ARCH="ppc64"
+    elif check_define __riscv ; then
+        ARCH="riscv64"
     else
         echo "This cpu is not supported by risu. Try -h. " >&2
         exit 1
@@ -139,7 +141,7 @@  Some influential environment variables:
                prefixed with the given string.
 
   ARCH         force target architecture instead of trying to detect it.
-               Valid values=[arm|aarch64|ppc64|ppc64le|m68k]
+               Valid values=[arm|aarch64|ppc64|ppc64le|m68k|riscv64]
 
   CC           C compiler command
   CFLAGS       C compiler flags