| Message ID | 20200429140003.7336-15-kraxel@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | acpi: i386 tweaks | expand |
On Wed, 29 Apr 2020 16:00:02 +0200 Gerd Hoffmann <kraxel@redhat.com> wrote: > Add helper function to add fw_cfg device, > also move code to hw/i386/fw_cfg.c. > > Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> > --- > hw/i386/fw_cfg.h | 1 + > hw/i386/acpi-build.c | 24 +----------------------- > hw/i386/fw_cfg.c | 28 ++++++++++++++++++++++++++++ > 3 files changed, 30 insertions(+), 23 deletions(-) > > diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h > index 9e742787792b..275f15c1c5e8 100644 > --- a/hw/i386/fw_cfg.h > +++ b/hw/i386/fw_cfg.h > @@ -25,5 +25,6 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms, > uint16_t apic_id_limit); > void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg); > void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg); > +void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg); > > #endif > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 643e875c05a5..a8b790021974 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1874,30 +1874,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > /* create fw_cfg node, unconditionally */ > { > - /* when using port i/o, the 8-bit data register *always* overlaps > - * with half of the 16-bit control register. Hence, the total size > - * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the > - * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ > - uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg), > - "dma_enabled", NULL) ? > - ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : > - FW_CFG_CTL_SIZE; > - > scope = aml_scope("\\_SB.PCI0"); > - dev = aml_device("FWCF"); > - > - aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); > - > - /* device present, functioning, decoding, not shown in UI */ > - aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); > - > - crs = aml_resource_template(); > - aml_append(crs, > - aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) > - ); > - aml_append(dev, aml_name_decl("_CRS", crs)); > - > - aml_append(scope, dev); > + fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); > aml_append(dsdt, scope); > } > > diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c > index da60ada59462..c55abfb01abb 100644 > --- a/hw/i386/fw_cfg.c > +++ b/hw/i386/fw_cfg.c > @@ -15,6 +15,7 @@ > #include "qemu/osdep.h" > #include "sysemu/numa.h" > #include "hw/acpi/acpi.h" > +#include "hw/acpi/aml-build.h" > #include "hw/firmware/smbios.h" > #include "hw/i386/fw_cfg.h" > #include "hw/timer/hpet.h" > @@ -179,3 +180,30 @@ void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) > *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); > fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); > } > + > +void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) > +{ > + /* > + * when using port i/o, the 8-bit data register *always* overlaps > + * with half of the 16-bit control register. Hence, the total size > + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the > + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 > + */ > + Object *obj = OBJECT(fw_cfg); > + uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? > + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : > + FW_CFG_CTL_SIZE; > + Aml *dev = aml_device("FWCF"); > + Aml *crs = aml_resource_template(); > + > + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); > + > + /* device present, functioning, decoding, not shown in UI */ > + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); > + > + aml_append(crs, > + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)); > + > + aml_append(dev, aml_name_decl("_CRS", crs)); > + aml_append(scope, dev); > +}
diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h index 9e742787792b..275f15c1c5e8 100644 --- a/hw/i386/fw_cfg.h +++ b/hw/i386/fw_cfg.h @@ -25,5 +25,6 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms, uint16_t apic_id_limit); void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg); void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg); +void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg); #endif diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 643e875c05a5..a8b790021974 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1874,30 +1874,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, /* create fw_cfg node, unconditionally */ { - /* when using port i/o, the 8-bit data register *always* overlaps - * with half of the 16-bit control register. Hence, the total size - * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the - * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ - uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg), - "dma_enabled", NULL) ? - ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : - FW_CFG_CTL_SIZE; - scope = aml_scope("\\_SB.PCI0"); - dev = aml_device("FWCF"); - - aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); - - /* device present, functioning, decoding, not shown in UI */ - aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); - - crs = aml_resource_template(); - aml_append(crs, - aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) - ); - aml_append(dev, aml_name_decl("_CRS", crs)); - - aml_append(scope, dev); + fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); aml_append(dsdt, scope); } diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index da60ada59462..c55abfb01abb 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -15,6 +15,7 @@ #include "qemu/osdep.h" #include "sysemu/numa.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" #include "hw/firmware/smbios.h" #include "hw/i386/fw_cfg.h" #include "hw/timer/hpet.h" @@ -179,3 +180,30 @@ void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); } + +void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) +{ + /* + * when using port i/o, the 8-bit data register *always* overlaps + * with half of the 16-bit control register. Hence, the total size + * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the + * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 + */ + Object *obj = OBJECT(fw_cfg); + uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? + ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : + FW_CFG_CTL_SIZE; + Aml *dev = aml_device("FWCF"); + Aml *crs = aml_resource_template(); + + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); + + /* device present, functioning, decoding, not shown in UI */ + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); + + aml_append(crs, + aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)); + + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); +}