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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z16sm8481824wrl.0.2020.04.22.05.45.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2020 05:45:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-5.0?] target/arm: Fix ID_MMFR4 value on AArch64 'max' CPU Date: Wed, 22 Apr 2020 13:45:01 +0100 Message-Id: <20200422124501.28015-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Desnogues , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In commit 41a4bf1feab098da4cd the added code to set the CNP field in ID_MMFR4 for the AArch64 'max' CPU had a typo where it used the wrong variable name, resulting in ID_MMFR4 fields AC2, XNX and LSM being wrong. Fix the typo. Fixes: 41a4bf1feab098da4cd Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Laurent Desnogues Reviewed-by: Philippe Mathieu-Daudé --- maybe 5.0 just because it's so trivial. I dunno... There's also an error where we use the uint32_t u variable to update the 64-bit ID_AA64DFR0 register, but that's harmless because as it happens the top 32 bits of that register are all zeroes anyway, so we can just fix that in 5.1. target/arm/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 62d36f9e8d3..95d0c8c101a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -705,7 +705,7 @@ static void aarch64_max_initfn(Object *obj) u = cpu->isar.id_mmfr4; u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ cpu->isar.id_mmfr4 = u; u = cpu->isar.id_aa64dfr0;