| Message ID | 20200420204203.13279-1-steplong@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement SVE2 scatter store insns | expand |
On 4/20/20 1:42 PM, Stephen Long wrote: > +static bool trans_ST1_zprz_sve2(DisasContext *s, arg_ST1_zprz_sve2 *a) > +{ > + gen_helper_gvec_mem_scatter *fn; > + bool be = s->be_data == MO_BE; > + bool mte = s->mte_active[0]; > + > + if (!dc_isar_feature(aa64_sve2, s) || a->esz < a->msz > + || (a->msz == 0 && a->scale)) { > + return false; > + } > + if (!sve_access_check(s)) { > + return true; > + } > + switch (a->esz) { > + case MO_32: > + fn = scatter_store_fn32[mte][be][a->xs][a->msz]; > + break; > + case MO_64: > + fn = scatter_store_fn64[mte][be][a->xs][a->msz]; > + break; > + default: > + g_assert_not_reached(); > + } > + do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, > + cpu_reg_sp(s, a->rn), a->msz, true, fn); > + return true; > +} I was thinking of something more along the lines of static bool STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) { if (!dc_isar_feature(aa64_sve2, s)) { return false; } return trans_ST1_zprz(s, a); } The fields should be identical, and so decodetree should pick the same type for 'a', underneath all of the typedefs. If decodetree cannot find a common argument set for the two insns, we might need to help it along, like we do with e.g. &rri_esz. I don't know without trying if that will be required. r~
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index dd987da648..6d0b8144c3 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1387,3 +1387,13 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx ### SVE2 floating point matrix multiply accumulate FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm + +### SVE2 Memory Store Group + +# SVE2 64-bit scatter non-temporal store (vector plus scalar) +ST1_zprz_sve2 1110010 .. 00 ..... 001 ... ..... ..... \ + @rprr_scatter_store xs=2 esz=3 scale=0 + +# SVE2 32-bit scatter non-temporal store (vector plus scalar) +ST1_zprz_sve2 1110010 .. 10 ..... 001 ... ..... ..... \ + @rprr_scatter_store xs=0 esz=2 scale=0 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 29532424c1..2919692dff 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6038,6 +6038,34 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) return true; } +static bool trans_ST1_zprz_sve2(DisasContext *s, arg_ST1_zprz_sve2 *a) +{ + gen_helper_gvec_mem_scatter *fn; + bool be = s->be_data == MO_BE; + bool mte = s->mte_active[0]; + + if (!dc_isar_feature(aa64_sve2, s) || a->esz < a->msz + || (a->msz == 0 && a->scale)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + switch (a->esz) { + case MO_32: + fn = scatter_store_fn32[mte][be][a->xs][a->msz]; + break; + case MO_64: + fn = scatter_store_fn64[mte][be][a->xs][a->msz]; + break; + default: + g_assert_not_reached(); + } + do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, + cpu_reg_sp(s, a->rn), a->msz, true, fn); + return true; +} + /* * Prefetches */
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store insns. 64-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT1W (vector plus scalar) * STNT1D (vector plus scalar) 32-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT1W (vector plus scalar) Signed-off-by: Stephen Long <steplong@quicinc.com> I'm not sure if this is the correct way to do this. --- target/arm/sve.decode | 10 ++++++++++ target/arm/translate-sve.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)