From patchwork Fri Apr 10 06:35:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenyi Qiang X-Patchwork-Id: 1268973 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48z7b958Mgz9sSX for ; Fri, 10 Apr 2020 16:36:53 +1000 (AEST) Received: from localhost ([::1]:59172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMnHX-0002Ke-Lk for incoming@patchwork.ozlabs.org; Fri, 10 Apr 2020 02:36:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34124) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMnFb-0007HO-5G for qemu-devel@nongnu.org; Fri, 10 Apr 2020 02:34:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jMnFZ-0007CI-EU for qemu-devel@nongnu.org; Fri, 10 Apr 2020 02:34:50 -0400 Received: from mga07.intel.com ([134.134.136.100]:42757) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jMnFZ-0007BO-5F for qemu-devel@nongnu.org; Fri, 10 Apr 2020 02:34:49 -0400 IronPort-SDR: b0c5s9RoRFOs2pR9DQ9Qx5vV8NvKe0RtBGGs0ai4xqlTJBv3W8JDbgWKHmdYixw49/CcztiRhJ 46o/s5LNjGrA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2020 23:34:43 -0700 IronPort-SDR: yzJyejpyJb1YGM0NOqERfxSn+tE76jivnloYYN1ZAWZx5kUHYxKEg/pLqEtYKmg2XZKUL0qbH9 FcZ+RTUd2Hiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,364,1580803200"; d="scan'208";a="425800265" Received: from chenyi-pc.sh.intel.com ([10.239.159.72]) by orsmga005.jf.intel.com with ESMTP; 09 Apr 2020 23:34:41 -0700 From: Chenyi Qiang To: Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v3 2/4] target/i386: add fast short REP MOV support Date: Fri, 10 Apr 2020 14:35:53 +0800 Message-Id: <20200410063555.2309-3-chenyi.qiang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200410063555.2309-1-chenyi.qiang@intel.com> References: <20200410063555.2309-1-chenyi.qiang@intel.com> X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 134.134.136.100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiaoyao Li , qemu-devel@nongnu.org, Robert Hoo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g Icelake and Tigerlake, expose it to the guest VM. Signed-off-by: Chenyi Qiang --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3ed7502e80..4bbe9f0948 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -984,7 +984,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = CPUID_FEATURE_WORD, .feat_names = { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", - NULL, NULL, NULL, NULL, + "fsrm", NULL, NULL, NULL, NULL, NULL, "md-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* pconfig */, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e818fc712a..d320265b92 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -770,6 +770,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) +/* Fast Short Rep Mov */ +#define CPUID_7_0_EDX_FSRM (1U << 4) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */