| Message ID | 20200408125816.955-5-miaoyubo@huawei.com |
|---|---|
| State | New |
| Headers | show |
| Series | pci_expander_brdige:acpi:Support pxb-pcie for ARM | expand |
On Wed, Apr 08, 2020 at 08:58:12PM +0800, Yubo Miao wrote: > From: miaoyubo <miaoyubo@huawei.com> > > The resources of pxbs and obtained by crs_build and the resources > used by pxbs would be moved form the resources defined for host-bridge. > > The resources for pxb are composed of the bar space of the > pci-bridge/pcie-root-port behined it and the config space of devices > behind it. > > Signed-off-by: miaoyubo <miaoyubo@huawei.com> A bunch of spelling/syntax mistakes in the log, pls spellcheck. Pls use the format Yubo Miao <miaoyubo@huawei.com> > --- > hw/arm/virt-acpi-build.c | 131 +++++++++++++++++++++++++++++++++------ > 1 file changed, 111 insertions(+), 20 deletions(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index e8ba09855c..7bcd04dfb7 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -49,6 +49,9 @@ > #include "kvm_arm.h" > #include "migration/vmstate.h" > > +#include "hw/arm/virt.h" > +#include "hw/pci/pci_bus.h" > +#include "hw/pci/pci_bridge.h" > #define ARM_SPI_BASE 32 > > static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) > @@ -266,19 +269,81 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) > } > > static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > - uint32_t irq, bool use_highmem, bool highmem_ecam) > + uint32_t irq, bool use_highmem, bool highmem_ecam, > + VirtMachineState *vms) > { > int ecam_id = VIRT_ECAM_ID(highmem_ecam); > - Aml *method, *crs; > + int i; > + Aml *method, *crs, *dev; > hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; > hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; > hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; > hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; > hwaddr base_ecam = memmap[ecam_id].base; > hwaddr size_ecam = memmap[ecam_id].size; > + CrsRangeEntry *entry; > + CrsRangeSet crs_range_set; > + > + crs_range_set_init(&crs_range_set); > int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; > + PCIHostState *s = OBJECT_CHECK(PCIHostState, > + object_resolve_path_type("", > + "pcie-host-bridge", NULL), > + TYPE_PCI_HOST_BRIDGE); Not TYPE_PCIE_HOST_BRIDGE? And what if it's ambiguous? > + > + PCIBus *bus = s->bus; > + /* start to construct the tables for pxb*/ coding style violation. weird that ehckpatch didn't notice it. > + if (bus) { > + QLIST_FOREACH(bus, &bus->child, sibling) { > + uint8_t bus_num = pci_bus_num(bus); > + uint8_t numa_node = pci_bus_numa_node(bus); > + > + if (!pci_bus_is_root(bus)) { > + continue; > + } > + /* > + * Coded up the MIN of the busNr defined for pxb-pcie, > + * the MIN - 1 would be the MAX bus number for the main > + * host bridge. Couldn't figure out this comment. Pls rephrase in some way so it's understandable. > + */ > + if (bus_num < nr_pcie_buses) { > + nr_pcie_buses = bus_num; > + } > + > + dev = aml_device("PC%.02X", bus_num); > + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); > + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); > + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); > + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); > + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); > + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); > + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); > + if (numa_node != NUMA_NODE_UNASSIGNED) { > + method = aml_method("_PXM", 0, AML_NOTSERIALIZED); > + aml_append(method, aml_return(aml_int(numa_node))); > + aml_append(dev, method); > + } > + > + acpi_dsdt_add_pci_route_table(dev, scope, irq); > + > + /* > + * Resources deined for PXBs are composed by the folling parts: > + * 1. The resources the pci-brige/pcie-root-port need. > + * 2. The resources the devices behind pxb need. > + */ syntax/grammar errors here too. > + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); > + aml_append(dev, aml_name_decl("_CRS", crs)); > + > + acpi_dsdt_add_pci_osc(dev, scope); > + > + aml_append(scope, dev); > + > + } > + } > > - Aml *dev = aml_device("%s", "PCI0"); > + /* start to construct the tables for main host bridge */ tables for the main. > + dev = aml_device("%s", "PCI0"); Make dev above local in scope, then this can stay unchanged. > aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); > aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); > aml_append(dev, aml_name_decl("_SEG", aml_int(0))); > @@ -299,25 +364,51 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, > 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, > nr_pcie_buses)); > - aml_append(rbuf, > - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, > - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, > - base_mmio + size_mmio - 1, 0x0000, size_mmio)); > - aml_append(rbuf, > - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, > - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, > - size_pio)); > + > + /* > + * Remove the resources used by PXBs. > + */ > + crs_replace_with_free_ranges(crs_range_set.mem_ranges, > + base_mmio, > + base_mmio + size_mmio - 1); > + for (i = 0; i < crs_range_set.mem_ranges->len; i++) { > + entry = g_ptr_array_index(crs_range_set.mem_ranges, i); > + aml_append(rbuf, > + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, > + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, > + entry->base, entry->limit, > + 0x0000, entry->limit - entry->base + 1)); > + } > + > + crs_replace_with_free_ranges(crs_range_set.io_ranges, > + 0x0000, > + size_pio - 1); > + for (i = 0; i < crs_range_set.io_ranges->len; i++) { > + entry = g_ptr_array_index(crs_range_set.io_ranges, i); > + aml_append(rbuf, > + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, > + AML_ENTIRE_RANGE, 0x0000, entry->base, > + entry->limit, base_pio, > + entry->limit - entry->base + 1)); > + } > + > > if (use_highmem) { > hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; > hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; > > - aml_append(rbuf, > - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, > - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, > - base_mmio_high, > - base_mmio_high + size_mmio_high - 1, 0x0000, > - size_mmio_high)); > + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, > + base_mmio_high, > + base_mmio_high + size_mmio_high - 1); > + for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { > + entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); > + aml_append(rbuf, > + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, > + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, > + entry->base, > + entry->limit, 0x0000, > + entry->limit - entry->base + 1)); > + } > } > > aml_append(method, aml_return(rbuf)); > @@ -335,6 +426,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, > aml_append(dev_res0, aml_name_decl("_CRS", crs)); > aml_append(dev, dev_res0); > aml_append(scope, dev); > + > + crs_range_set_free(&crs_range_set); > } > > static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, > @@ -746,7 +839,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], > (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); > acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), > - vms->highmem, vms->highmem_ecam); > + vms->highmem, vms->highmem_ecam, vms); > if (vms->acpi_dev) { > build_ged_aml(scope, "\\_SB."GED_DEVICE, > HOTPLUG_HANDLER(vms->acpi_dev), > @@ -798,7 +891,6 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) > unsigned dsdt, xsdt; > GArray *tables_blob = tables->table_data; > MachineState *ms = MACHINE(vms); > - > table_offsets = g_array_new(false, true /* clear */, > sizeof(uint32_t)); > this empty line didn't hurt > @@ -952,7 +1044,6 @@ void virt_acpi_setup(VirtMachineState *vms) > build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, > build_state, tables.rsdp, > ACPI_BUILD_RSDP_FILE, 0); > - > qemu_register_reset(virt_acpi_build_reset, build_state); > virt_acpi_build_reset(build_state); > vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); this line didn't hurt either. > -- > 2.19.1 >
Thanks so much for such a careful review!! > -----Original Message----- > From: Michael S. Tsirkin [mailto:mst@redhat.com] > Sent: Monday, May 4, 2020 10:01 PM > To: miaoyubo <miaoyubo@huawei.com> > Cc: peter.maydell@linaro.org; shannon.zhaosl@gmail.com; > lersek@redhat.com; imammedo@redhat.com; qemu-devel@nongnu.org; > berrange@redhat.com; Xiexiangyou <xiexiangyou@huawei.com> > Subject: Re: [PATCH v6 4/8] acpi: Refactor the source of host bridge and build > tables for pxb > > On Wed, Apr 08, 2020 at 08:58:12PM +0800, Yubo Miao wrote: > > From: miaoyubo <miaoyubo@huawei.com> > > > > The resources of pxbs and obtained by crs_build and the resources used > > by pxbs would be moved form the resources defined for host-bridge. > > > > The resources for pxb are composed of the bar space of the > > pci-bridge/pcie-root-port behined it and the config space of devices > > behind it. > > > > Signed-off-by: miaoyubo <miaoyubo@huawei.com> > > A bunch of spelling/syntax mistakes in the log, pls spellcheck. > > Pls use the format > Yubo Miao <miaoyubo@huawei.com> > > > Thanks for pointing out the mistakes! > > --- > > hw/arm/virt-acpi-build.c | 131 > > +++++++++++++++++++++++++++++++++------ > > 1 file changed, 111 insertions(+), 20 deletions(-) > > > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index > > e8ba09855c..7bcd04dfb7 100644 > > --- a/hw/arm/virt-acpi-build.c > > +++ b/hw/arm/virt-acpi-build.c > > @@ -49,6 +49,9 @@ > > #include "kvm_arm.h" > > #include "migration/vmstate.h" > > > > +#include "hw/arm/virt.h" > > +#include "hw/pci/pci_bus.h" > > +#include "hw/pci/pci_bridge.h" > > #define ARM_SPI_BASE 32 > > > > static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -266,19 > > +269,81 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) } > > > > static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry > *memmap, > > - uint32_t irq, bool use_highmem, bool highmem_ecam) > > + uint32_t irq, bool use_highmem, bool highmem_ecam, > > + VirtMachineState *vms) > > { > > int ecam_id = VIRT_ECAM_ID(highmem_ecam); > > - Aml *method, *crs; > > + int i; > > + Aml *method, *crs, *dev; > > hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; > > hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; > > hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; > > hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; > > hwaddr base_ecam = memmap[ecam_id].base; > > hwaddr size_ecam = memmap[ecam_id].size; > > + CrsRangeEntry *entry; > > + CrsRangeSet crs_range_set; > > + > > + crs_range_set_init(&crs_range_set); > > int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; > > + PCIHostState *s = OBJECT_CHECK(PCIHostState, > > + object_resolve_path_type("", > > + "pcie-host-bridge", NULL), > > + TYPE_PCI_HOST_BRIDGE); > > Not TYPE_PCIE_HOST_BRIDGE? And what if it's ambiguous? > > Yes, TYPE_PCI_HOST_BRIDGE is ambiguous, I would fix it. > > + > > + PCIBus *bus = s->bus; > > + /* start to construct the tables for pxb*/ > > > coding style violation. weird that ehckpatch didn't notice it. > Thanks for such a careful review! > > + if (bus) { > > + QLIST_FOREACH(bus, &bus->child, sibling) { > > + uint8_t bus_num = pci_bus_num(bus); > > + uint8_t numa_node = pci_bus_numa_node(bus); > > + > > + if (!pci_bus_is_root(bus)) { > > + continue; > > + } > > + /* > > + * Coded up the MIN of the busNr defined for pxb-pcie, > > + * the MIN - 1 would be the MAX bus number for the main > > + * host bridge. > > > Couldn't figure out this comment. Pls rephrase in some way so it's > understandable. > How about /* 0 - (nr_pcie_buses - 1) is the bus range for the main * host-bridge and it equals the MIN of the * busNr defined for pxb-pcie*/ > > + */ > > + if (bus_num < nr_pcie_buses) { > > + nr_pcie_buses = bus_num; > > + } > > + > > + } > > + > > + acpi_dsdt_add_pci_route_table(dev, scope, irq); > > + > > + /* > > + * Resources deined for PXBs are composed by the folling parts: > > + * 1. The resources the pci-brige/pcie-root-port need. > > + * 2. The resources the devices behind pxb need. > > + */ > > > syntax/grammar errors here too. > Sorry for the syntax error! > > + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), > &crs_range_set); > > + aml_append(dev, aml_name_decl("_CRS", crs)); > > + > > + acpi_dsdt_add_pci_osc(dev, scope); > > + > > + aml_append(scope, dev); > > + > > + } > > + } > > > > - Aml *dev = aml_device("%s", "PCI0"); > > + /* start to construct the tables for main host bridge */ > > tables for the main. > > Yes, tables for the main is better. > > > + dev = aml_device("%s", "PCI0"); > > > Make dev above local in scope, then this can stay unchanged. > Sure. > > aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); > > aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); > > aml_append(dev, aml_name_decl("_SEG", aml_int(0))); @@ -299,25 > > +364,51 @@ static void acpi_dsdt_add_pci(Aml *scope, const > MemMapEntry *memmap, > > aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, > AML_POS_DECODE, > > 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, > > nr_pcie_buses)); > > - aml_append(rbuf, > > - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, > AML_MAX_FIXED, > > unsigned dsdt, xsdt; > > GArray *tables_blob = tables->table_data; > > MachineState *ms = MACHINE(vms); > > - > > table_offsets = g_array_new(false, true /* clear */, > > sizeof(uint32_t)); > > > > this empty line didn't hurt > I would keep it. > > @@ -952,7 +1044,6 @@ void virt_acpi_setup(VirtMachineState *vms) > > build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, > > build_state, tables.rsdp, > > ACPI_BUILD_RSDP_FILE, > > 0); > > - > > qemu_register_reset(virt_acpi_build_reset, build_state); > > virt_acpi_build_reset(build_state); > > vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); > > > this line didn't hurt either. > I would keep it > > -- > > 2.19.1 > > Regards, Miao
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e8ba09855c..7bcd04dfb7 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -49,6 +49,9 @@ #include "kvm_arm.h" #include "migration/vmstate.h" +#include "hw/arm/virt.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" #define ARM_SPI_BASE 32 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -266,19 +269,81 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) } static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem_ecam) + uint32_t irq, bool use_highmem, bool highmem_ecam, + VirtMachineState *vms) { int ecam_id = VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs; + int i; + Aml *method, *crs, *dev; hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam = memmap[ecam_id].base; hwaddr size_ecam = memmap[ecam_id].size; + CrsRangeEntry *entry; + CrsRangeSet crs_range_set; + + crs_range_set_init(&crs_range_set); int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; + PCIHostState *s = OBJECT_CHECK(PCIHostState, + object_resolve_path_type("", + "pcie-host-bridge", NULL), + TYPE_PCI_HOST_BRIDGE); + + PCIBus *bus = s->bus; + /* start to construct the tables for pxb*/ + if (bus) { + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num = pci_bus_num(bus); + uint8_t numa_node = pci_bus_numa_node(bus); + + if (!pci_bus_is_root(bus)) { + continue; + } + /* + * Coded up the MIN of the busNr defined for pxb-pcie, + * the MIN - 1 would be the MAX bus number for the main + * host bridge. + */ + if (bus_num < nr_pcie_buses) { + nr_pcie_buses = bus_num; + } + + dev = aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); + if (numa_node != NUMA_NODE_UNASSIGNED) { + method = aml_method("_PXM", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(numa_node))); + aml_append(dev, method); + } + + acpi_dsdt_add_pci_route_table(dev, scope, irq); + + /* + * Resources deined for PXBs are composed by the folling parts: + * 1. The resources the pci-brige/pcie-root-port need. + * 2. The resources the devices behind pxb need. + */ + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + aml_append(dev, aml_name_decl("_CRS", crs)); + + acpi_dsdt_add_pci_osc(dev, scope); + + aml_append(scope, dev); + + } + } - Aml *dev = aml_device("%s", "PCI0"); + /* start to construct the tables for main host bridge */ + dev = aml_device("%s", "PCI0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); aml_append(dev, aml_name_decl("_SEG", aml_int(0))); @@ -299,25 +364,51 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, nr_pcie_buses)); - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, - size_pio)); + + /* + * Remove the resources used by PXBs. + */ + crs_replace_with_free_ranges(crs_range_set.mem_ranges, + base_mmio, + base_mmio + size_mmio - 1); + for (i = 0; i < crs_range_set.mem_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_ranges, i); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, entry->limit, + 0x0000, entry->limit - entry->base + 1)); + } + + crs_replace_with_free_ranges(crs_range_set.io_ranges, + 0x0000, + size_pio - 1); + for (i = 0; i < crs_range_set.io_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.io_ranges, i); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, entry->base, + entry->limit, base_pio, + entry->limit - entry->base + 1)); + } + if (use_highmem) { hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + base_mmio_high, + base_mmio_high + size_mmio_high - 1); + for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, + entry->limit, 0x0000, + entry->limit - entry->base + 1)); + } } aml_append(method, aml_return(rbuf)); @@ -335,6 +426,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_append(dev_res0, aml_name_decl("_CRS", crs)); aml_append(dev, dev_res0); aml_append(scope, dev); + + crs_range_set_free(&crs_range_set); } static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, @@ -746,7 +839,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), - vms->highmem, vms->highmem_ecam); + vms->highmem, vms->highmem_ecam, vms); if (vms->acpi_dev) { build_ged_aml(scope, "\\_SB."GED_DEVICE, HOTPLUG_HANDLER(vms->acpi_dev), @@ -798,7 +891,6 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) unsigned dsdt, xsdt; GArray *tables_blob = tables->table_data; MachineState *ms = MACHINE(vms); - table_offsets = g_array_new(false, true /* clear */, sizeof(uint32_t)); @@ -952,7 +1044,6 @@ void virt_acpi_setup(VirtMachineState *vms) build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); - qemu_register_reset(virt_acpi_build_reset, build_state); virt_acpi_build_reset(build_state); vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);