Message ID | 20200330153633.15298-27-zhiwei_liu@c-sky.com |
---|---|
State | New |
Headers | show |
Series | target/riscv: support vector extension v0.7.1 | expand |
On Mon, Mar 30, 2020 at 9:29 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/helper.h | 9 ++ > target/riscv/insn32.decode | 2 + > target/riscv/insn_trans/trans_rvv.inc.c | 4 + > target/riscv/vector_helper.c | 107 ++++++++++++++++++++++++ > 4 files changed, 122 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 32d549ce36..e6cae1b59c 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -736,3 +736,12 @@ DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) > + > +DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index e617d7bd60..633f782fbf 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -422,6 +422,8 @@ vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm > vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm > vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm > vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm > +vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm > +vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index a7cf4f4614..08a8444b46 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -1778,3 +1778,7 @@ GEN_OPIVV_TRANS(vasub_vv, opivv_check) > GEN_OPIVX_TRANS(vaadd_vx, opivx_check) > GEN_OPIVX_TRANS(vasub_vx, opivx_check) > GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) > + > +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ > +GEN_OPIVV_TRANS(vsmul_vv, opivv_check) > +GEN_OPIVX_TRANS(vsmul_vx, opivx_check) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 784993b5f6..23868fb1b2 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -2596,3 +2596,110 @@ GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb) > GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh) > GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl) > GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq) > + > +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ > +static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) > +{ > + uint8_t round; > + int16_t res; > + > + res = (int16_t)a * (int16_t)b; > + round = get_round(vxrm, res, 7); > + res = (res >> 7) + round; > + > + if (res > INT8_MAX) { > + env->vxsat = 0x1; > + return INT8_MAX; > + } else if (res < INT8_MIN) { > + env->vxsat = 0x1; > + return INT8_MIN; > + } else { > + return res; > + } > +} > + > +static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) > +{ > + uint8_t round; > + int32_t res; > + > + res = (int32_t)a * (int32_t)b; > + round = get_round(vxrm, res, 15); > + res = (res >> 15) + round; > + > + if (res > INT16_MAX) { > + env->vxsat = 0x1; > + return INT16_MAX; > + } else if (res < INT16_MIN) { > + env->vxsat = 0x1; > + return INT16_MIN; > + } else { > + return res; > + } > +} > + > +static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) > +{ > + uint8_t round; > + int64_t res; > + > + res = (int64_t)a * (int64_t)b; > + round = get_round(vxrm, res, 31); > + res = (res >> 31) + round; > + > + if (res > INT32_MAX) { > + env->vxsat = 0x1; > + return INT32_MAX; > + } else if (res < INT32_MIN) { > + env->vxsat = 0x1; > + return INT32_MIN; > + } else { > + return res; > + } > +} > + > +static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) > +{ > + uint8_t round; > + uint64_t hi_64, lo_64; > + int64_t res; > + > + if (a == INT64_MIN && b == INT64_MIN) { > + env->vxsat = 1; > + return INT64_MAX; > + } > + > + muls64(&lo_64, &hi_64, a, b); > + round = get_round(vxrm, lo_64, 63); > + /* > + * Cannot overflow, as there are always > + * 2 sign bits after multiply. > + */ > + res = (hi_64 << 1) | (lo_64 >> 63); > + if (round) { > + if (res == INT64_MAX) { > + env->vxsat = 1; > + } else { > + res += 1; > + } > + } > + return res; > +} > + > +RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) > +RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) > +RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) > +RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) > +GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1, clearb) > +GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2, clearh) > +GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4, clearl) > +GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8, clearq) > + > +RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) > +RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) > +RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) > +RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) > +GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb) > +GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh) > +GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl) > +GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq) > -- > 2.23.0 >
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 32d549ce36..e6cae1b59c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -736,3 +736,12 @@ DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e617d7bd60..633f782fbf 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -422,6 +422,8 @@ vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm +vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm +vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index a7cf4f4614..08a8444b46 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1778,3 +1778,7 @@ GEN_OPIVV_TRANS(vasub_vv, opivv_check) GEN_OPIVX_TRANS(vaadd_vx, opivx_check) GEN_OPIVX_TRANS(vasub_vx, opivx_check) GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +GEN_OPIVV_TRANS(vsmul_vv, opivv_check) +GEN_OPIVX_TRANS(vsmul_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 784993b5f6..23868fb1b2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2596,3 +2596,110 @@ GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb) GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) +{ + uint8_t round; + int16_t res; + + res = (int16_t)a * (int16_t)b; + round = get_round(vxrm, res, 7); + res = (res >> 7) + round; + + if (res > INT8_MAX) { + env->vxsat = 0x1; + return INT8_MAX; + } else if (res < INT8_MIN) { + env->vxsat = 0x1; + return INT8_MIN; + } else { + return res; + } +} + +static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) +{ + uint8_t round; + int32_t res; + + res = (int32_t)a * (int32_t)b; + round = get_round(vxrm, res, 15); + res = (res >> 15) + round; + + if (res > INT16_MAX) { + env->vxsat = 0x1; + return INT16_MAX; + } else if (res < INT16_MIN) { + env->vxsat = 0x1; + return INT16_MIN; + } else { + return res; + } +} + +static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) +{ + uint8_t round; + int64_t res; + + res = (int64_t)a * (int64_t)b; + round = get_round(vxrm, res, 31); + res = (res >> 31) + round; + + if (res > INT32_MAX) { + env->vxsat = 0x1; + return INT32_MAX; + } else if (res < INT32_MIN) { + env->vxsat = 0x1; + return INT32_MIN; + } else { + return res; + } +} + +static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) +{ + uint8_t round; + uint64_t hi_64, lo_64; + int64_t res; + + if (a == INT64_MIN && b == INT64_MIN) { + env->vxsat = 1; + return INT64_MAX; + } + + muls64(&lo_64, &hi_64, a, b); + round = get_round(vxrm, lo_64, 63); + /* + * Cannot overflow, as there are always + * 2 sign bits after multiply. + */ + res = (hi_64 << 1) | (lo_64 >> 63); + if (round) { + if (res == INT64_MAX) { + env->vxsat = 1; + } else { + res += 1; + } + } + return res; +} + +RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) +RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) +RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) +RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) +GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1, clearb) +GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2, clearh) +GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4, clearl) +GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) +RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) +RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) +RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) +GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb) +GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh) +GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl) +GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c | 107 ++++++++++++++++++++++++ 4 files changed, 122 insertions(+)