diff mbox series

[3/3] target/mips: Add loongson gs464 core

Message ID 20200325100520.206210-4-jiaxun.yang@flygoat.com
State New
Headers show
Series target/mips: Add loongson gs464 core | expand

Commit Message

Jiaxun Yang March 25, 2020, 10:05 a.m. UTC 
GS464 is the core we can found in Loongson-3A1000 processor with
MIPS64R2 as baseline ISA and Loongson self defined MMI & EXT ASE.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/translate_init.inc.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 6d145a905a..4e1eb5a2e4 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -830,7 +830,30 @@  const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
         .mmu_type = MMU_TYPE_R4000,
     },
-
+    {
+        .name = "gs464",
+        .CP0_PRid = 0x6305,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+                       (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+                       (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+                       (1 << CP0C1_C2) | (1 << CP0C1_PC) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2 | (1 << CP0C2_SU) | (6 << CP0C2_SU) |
+                        (4 << CP0C2_SU) | (3 << CP0C2_SU),
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+        .CP0_PageGrain = (1 << CP0PG_ELPA),
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x76FBFFFF,
+        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_PS) | (1 << FCR0_L) |
+                    (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
+                    (0x01 << FCR0_PRID) | (0x1 << FCR0_REV),
+        .SEGBITS = 42,
+        .PABITS = 48,
+        .insn_flags = CPU_MIPS64R2 | ASE_LOONGSON_MMI | ASE_LOONGSON_EXT,
+        .mmu_type = MMU_TYPE_R4000,
+    },
 #endif
 };
 const int mips_defs_number = ARRAY_SIZE(mips_defs);