| Message ID | 20200317150653.9008-62-zhiwei_liu@c-sky.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: support vector extension v0.7.1 | expand |
On Tue, Mar 17, 2020 at 10:09 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Vector extension is default off. The only way to use vector extension is > 1. use cpu rv32 or rv64 > 2. turn on it by command line > "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". > > vlen is the vector register length, default value is 128 bit. > elen is the max operator size in bits, default value is 64 bit. > vext_spec is the vector specification version, default value is v0.7.1. > These properties can be specified with other values. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++++- > target/riscv/cpu.h | 2 ++ > 2 files changed, 45 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6e4135583d..92cbcf1a2d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -395,7 +395,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > > set_priv_version(env, priv_version); > - set_vext_version(env, vext_version); > set_resetvec(env, DEFAULT_RSTVEC); > > if (cpu->cfg.mmu) { > @@ -463,6 +462,45 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_h) { > target_misa |= RVH; > } > + if (cpu->cfg.ext_v) { > + target_misa |= RVV; > + if (!is_power_of_2(cpu->cfg.vlen)) { > + error_setg(errp, > + "Vector extension VLEN must be power of 2"); > + return; > + } > + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { > + error_setg(errp, > + "Vector extension implementation only supports VLEN " > + "in the range [128, %d]", RV_VLEN_MAX); > + return; > + } > + if (!is_power_of_2(cpu->cfg.elen)) { > + error_setg(errp, > + "Vector extension ELEN must be power of 2"); > + return; > + } > + if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { > + error_setg(errp, > + "Vector extension implementation only supports ELEN " > + "in the range [8, 64]"); > + return; > + } > + if (cpu->cfg.vext_spec) { > + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { > + vext_version = VEXT_VERSION_0_07_1; > + } else { > + error_setg(errp, > + "Unsupported vector spec version '%s'", > + cpu->cfg.vext_spec); > + return; > + } > + } else { > + qemu_log("vector verison is not specified, " > + "use the default value v0.7.1\n"); > + } > + set_vext_version(env, vext_version); > + } > > set_misa(env, RVXLEN | target_misa); > } > @@ -500,10 +538,14 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > /* This is experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > + DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f42f075024..42ab0f141a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -285,12 +285,14 @@ typedef struct RISCVCPU { > bool ext_s; > bool ext_u; > bool ext_h; > + bool ext_v; > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > > char *priv_spec; > char *user_spec; > + char *vext_spec; > uint16_t vlen; > uint16_t elen; > bool mmu; > -- > 2.23.0 >
On 3/17/20 8:06 AM, LIU Zhiwei wrote: > Vector extension is default off. The only way to use vector extension is > 1. use cpu rv32 or rv64 > 2. turn on it by command line > "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". > > vlen is the vector register length, default value is 128 bit. > elen is the max operator size in bits, default value is 64 bit. > vext_spec is the vector specification version, default value is v0.7.1. > These properties can be specified with other values. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++++- > target/riscv/cpu.h | 2 ++ > 2 files changed, 45 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6e4135583d..92cbcf1a2d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -395,7 +395,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_priv_version(env, priv_version); - set_vext_version(env, vext_version); set_resetvec(env, DEFAULT_RSTVEC); if (cpu->cfg.mmu) { @@ -463,6 +462,45 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_v) { + target_misa |= RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { + vext_version = VEXT_VERSION_0_07_1; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector verison is not specified, " + "use the default value v0.7.1\n"); + } + set_vext_version(env, vext_version); + } set_misa(env, RVXLEN | target_misa); } @@ -500,10 +538,14 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f42f075024..42ab0f141a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,12 +285,14 @@ typedef struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_v; bool ext_counters; bool ext_ifencei; bool ext_icsr; char *priv_spec; char *user_spec; + char *vext_spec; uint16_t vlen; uint16_t elen; bool mmu;
Vector extension is default off. The only way to use vector extension is 1. use cpu rv32 or rv64 2. turn on it by command line "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. These properties can be specified with other values. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 2 ++ 2 files changed, 45 insertions(+), 1 deletion(-)