diff mbox series

[v4] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()

Message ID 20200313123242.13236-1-kuhn.chenqun@huawei.com
State New
Headers show
Series [v4] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write() | expand

Commit Message

Chenqun (kuhn) March 13, 2020, 12:32 p.m. UTC
The current code causes clang static code analyzer generate warning:
hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
        value = value & 0x0000000f;
        ^       ~~~~~~~~~~~~~~~~~~
hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
        value = value & 0x000000fd;
        ^       ~~~~~~~~~~~~~~~~~~

According to the definition of the function, the two “value” assignments
 should be written to registers.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
---
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Peter Chubb <peter.chubb@nicta.com.au>

v1->v2:
  The register 'ENET_TGSR' write-1-to-clear timer flag.
  The register 'ENET_TCSRn' 7bit(TF) write-1-to-clear timer flag.

v2->v3:
  Optimize code style, based on discussions with Peter.

v3->v4:
  Delete reserved bits write zero(Base on Peter's comments).
---
 hw/net/imx_fec.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Peter Maydell March 13, 2020, 2:28 p.m. UTC | #1
On Fri, 13 Mar 2020 at 12:33, Chen Qun <kuhn.chenqun@huawei.com> wrote:
>
> The current code causes clang static code analyzer generate warning:
> hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
>         value = value & 0x0000000f;
>         ^       ~~~~~~~~~~~~~~~~~~
> hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
>         value = value & 0x000000fd;
>         ^       ~~~~~~~~~~~~~~~~~~
>
> According to the definition of the function, the two “value” assignments
>  should be written to registers.
>
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>


Applied to target-arm.next; thanks for working through the code
review process.

-- PMM
Chenqun (kuhn) March 14, 2020, 3:15 a.m. UTC | #2
>-----Original Message-----
>From: Peter Maydell [mailto:peter.maydell@linaro.org]
>Sent: Friday, March 13, 2020 10:29 PM
>To: Chenqun (kuhn) <kuhn.chenqun@huawei.com>
>Cc: QEMU Developers <qemu-devel@nongnu.org>; QEMU Trivial <qemu-
>trivial@nongnu.org>; Zhanghailiang <zhang.zhanghailiang@huawei.com>;
>Euler Robot <euler.robot@huawei.com>; Jason Wang
><jasowang@redhat.com>; Peter Chubb <peter.chubb@nicta.com.au>
>Subject: Re: [PATCH v4] hw/net/imx_fec: write TGSR and TCSR3 in
>imx_enet_write()
>
>On Fri, 13 Mar 2020 at 12:33, Chen Qun <kuhn.chenqun@huawei.com> wrote:
>>
>> The current code causes clang static code analyzer generate warning:
>> hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
>>         value = value & 0x0000000f;
>>         ^       ~~~~~~~~~~~~~~~~~~
>> hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
>>         value = value & 0x000000fd;
>>         ^       ~~~~~~~~~~~~~~~~~~
>>
>> According to the definition of the function, the two “value”
>> assignments  should be written to registers.
>>
>> Reported-by: Euler Robot <euler.robot@huawei.com>
>> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
>
>
>Applied to target-arm.next; thanks for working through the code review
>process.
>

Thank you for your detailed review and effective suggestions, too.
diff mbox series

Patch

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 6a124a154a..5c145a8197 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -855,13 +855,15 @@  static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
         break;
     case ENET_TGSR:
         /* implement clear timer flag */
-        value = value & 0x0000000f;
+        s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
         break;
     case ENET_TCSR0:
     case ENET_TCSR1:
     case ENET_TCSR2:
     case ENET_TCSR3:
-        value = value & 0x000000fd;
+        s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
+        s->regs[index] &= ~0x0000007d; /* writable fields */
+        s->regs[index] |= (value & 0x0000007d);
         break;
     case ENET_TCCR0:
     case ENET_TCCR1: