From patchwork Wed Mar 11 13:51:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 1252933 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=FnEs27gm; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48ctk05jBCz9sPJ for ; Thu, 12 Mar 2020 00:54:32 +1100 (AEDT) Received: from localhost ([::1]:52452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jC1oc-0007UZ-LN for incoming@patchwork.ozlabs.org; Wed, 11 Mar 2020 09:54:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35717) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jC1mE-0002qw-HZ for qemu-devel@nongnu.org; Wed, 11 Mar 2020 09:52:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jC1mD-0001fg-7T for qemu-devel@nongnu.org; Wed, 11 Mar 2020 09:52:02 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:42275 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jC1mD-0001ev-3O for qemu-devel@nongnu.org; Wed, 11 Mar 2020 09:52:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1583934720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zl9FDtxwOI/FksilYChFV1G9aFjsIXI5j5prCQSwE+w=; b=FnEs27gm6InnDp45riPMoeZgjiXCIcrYBFjW03LWp2jOLbDzm/chiwceZ9Ztx+4firk2Fx X/K5CHfe6VEJZ7Hj2V3ygesljG3LrIGpjLtT1g0gtEjQxnhQ67b3OSEUeBfEBJDaj8VSS0 Uey//Z1+iXGSJTMLfm5HbMYoq/E2ozE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-434-stmFc2VFMl6MkBlKwYFiCg-1; Wed, 11 Mar 2020 09:51:57 -0400 X-MC-Unique: stmFc2VFMl6MkBlKwYFiCg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 74D828017CC; Wed, 11 Mar 2020 13:51:55 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.36.118.12]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1AA1D5C13D; Wed, 11 Mar 2020 13:51:50 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v6 05/13] arm/arm64: gicv3: Set the LPI config and pending tables Date: Wed, 11 Mar 2020 14:51:09 +0100 Message-Id: <20200311135117.9366-6-eric.auger@redhat.com> In-Reply-To: <20200311135117.9366-1-eric.auger@redhat.com> References: <20200311135117.9366-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table. Also introduce a helper routine that allows to set the pending table bit for a given LPI and macros to set/get its configuration. Signed-off-by: Eric Auger Reviewed-by: Zenghui Yu --- v5 -> v6: - fix the assert() - remove GICR_PROPBASER_IDBITS_MASK - remove gicv3_lpi_set_config and gicv3_lpi_get_config declarations and move macros in this patch v4 -> v5: - Moved some reformattings previously done in "arm/arm64: ITS: its_enable_defaults", in this patch - added assert(!gicv3_redist_base()) in gicv3_lpi_alloc_tables() - revert for_each_present_cpu() change v2 -> v3: - Move the helpers in lib/arm/gic-v3.c and prefix them with "gicv3_" and add _lpi prefix too v1 -> v2: - remove memory attributes --- lib/arm/asm/gic-v3.h | 17 ++++++++++++++ lib/arm/gic-v3.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 47df051..fedffa8 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -50,6 +50,13 @@ #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT) +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define LPI_PROP_GROUP1 (1 << 1) +#define LPI_PROP_ENABLED (1 << 0) +#define LPI_PROP_DEFAULT_PRIO 0xa0 +#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | LPI_PROP_ENABLED) + #include #ifndef __ASSEMBLY__ @@ -66,6 +73,8 @@ struct gicv3_data { void *dist_base; void *redist_bases[GICV3_NR_REDISTS]; void *redist_base[NR_CPUS]; + u8 *lpi_prop; + void *lpi_pend[NR_CPUS]; unsigned int irq_nr; }; extern struct gicv3_data gicv3_data; @@ -82,6 +91,8 @@ extern void gicv3_write_eoir(u32 irqstat); extern void gicv3_ipi_send_single(int irq, int cpu); extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest); extern void gicv3_set_redist_base(size_t stride); +extern void gicv3_lpi_set_clr_pending(int rdist, int n, bool set); +extern void gicv3_lpi_alloc_tables(void); static inline void gicv3_do_wait_for_rwp(void *base) { @@ -127,5 +138,11 @@ static inline u64 mpidr_uncompress(u32 compressed) return mpidr; } +#define gicv3_lpi_set_config(intid, value) ({ \ + gicv3_data.lpi_prop[LPI_OFFSET(intid)] = value; \ +}) + +#define gicv3_lpi_get_config(intid) (gicv3_data.lpi_prop[LPI_OFFSET(intid)]) + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_H_ */ diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index feecb5e..6cf1d1d 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -5,6 +5,7 @@ */ #include #include +#include void gicv3_set_redist_base(size_t stride) { @@ -147,3 +148,55 @@ void gicv3_ipi_send_single(int irq, int cpu) cpumask_set_cpu(cpu, &dest); gicv3_ipi_send_mask(irq, &dest); } + +#if defined(__aarch64__) + +/* + * alloc_lpi_tables - Allocate LPI config and pending tables + * and set PROPBASER (shared by all rdistributors) and per + * redistributor PENDBASER. + * + * gicv3_set_redist_base() must be called before + */ +void gicv3_lpi_alloc_tables(void) +{ + unsigned long n = SZ_64K >> PAGE_SHIFT; + unsigned long order = fls(n); + u64 prop_val; + int cpu; + + assert(gicv3_redist_base()); + + gicv3_data.lpi_prop = alloc_pages(order); + + /* ID bits = 13, ie. up to 14b LPI INTID */ + prop_val = (u64)(virt_to_phys(gicv3_data.lpi_prop)) | 13; + + for_each_present_cpu(cpu) { + u64 pend_val; + void *ptr; + + ptr = gicv3_data.redist_base[cpu]; + + writeq(prop_val, ptr + GICR_PROPBASER); + + gicv3_data.lpi_pend[cpu] = alloc_pages(order); + pend_val = (u64)(virt_to_phys(gicv3_data.lpi_pend[cpu])); + writeq(pend_val, ptr + GICR_PENDBASER); + } +} + +void gicv3_lpi_set_clr_pending(int rdist, int n, bool set) +{ + u8 *ptr = gicv3_data.lpi_pend[rdist]; + u8 mask = 1 << (n % 8), byte; + + ptr += (n / 8); + byte = *ptr; + if (set) + byte |= mask; + else + byte &= ~mask; + *ptr = byte; +} +#endif /* __aarch64__ */