@@ -59,6 +59,10 @@
#define LPI_PROP_DEFAULT_PRIO 0xa0
#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | LPI_PROP_ENABLED)
+#define LPI_ID_BASE 8192
+#define LPI(lpi) ((lpi) + LPI_ID_BASE)
+#define LPI_OFFSET(intid) ((intid) - LPI_ID_BASE)
+
#include <asm/arch_gicv3.h>
#ifndef __ASSEMBLY__
@@ -97,6 +101,8 @@ extern void gicv3_lpi_set_config(int n, u8 val);
extern u8 gicv3_lpi_get_config(int n);
extern void gicv3_lpi_set_clr_pending(int rdist, int n, bool set);
extern void gicv3_lpi_alloc_tables(void);
+extern void gicv3_lpi_rdist_enable(int redist);
+extern void gicv3_lpi_rdist_disable(int redist);
static inline void gicv3_do_wait_for_rwp(void *base)
{
@@ -142,5 +148,12 @@ static inline u64 mpidr_uncompress(u32 compressed)
return mpidr;
}
+#define gicv3_lpi_set_config(intid, value) ({ \
+ gicv3_data.lpi_prop[LPI_OFFSET(intid)] = value; \
+})
+
+#define gicv3_lpi_get_config(intid) (gicv3_data.lpi_prop[LPI_OFFSET(intid)])
+
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_H_ */
@@ -199,4 +199,29 @@ void gicv3_lpi_set_clr_pending(int rdist, int n, bool set)
byte &= ~mask;
*ptr = byte;
}
+
+static void gicv3_lpi_rdist_ctrl(u32 redist, bool set)
+{
+ void *ptr;
+ u64 val;
+
+ assert(redist < nr_cpus);
+
+ ptr = gicv3_data.redist_base[redist];
+ val = readl(ptr + GICR_CTLR);
+ if (set)
+ val |= GICR_CTLR_ENABLE_LPIS;
+ else
+ val &= ~GICR_CTLR_ENABLE_LPIS;
+ writel(val, ptr + GICR_CTLR);
+}
+
+void gicv3_lpi_rdist_enable(int redist)
+{
+ gicv3_lpi_rdist_ctrl(redist, true);
+}
+void gicv3_lpi_rdist_disable(int redist)
+{
+ gicv3_lpi_rdist_ctrl(redist, false);
+}
#endif /* __aarch64__ */
@@ -88,5 +88,6 @@ extern struct its_data its_data;
extern void its_parse_typer(void);
extern void its_init(void);
extern int its_baser_lookup(int i, struct its_baser *baser);
+extern void its_enable_defaults(void);
#endif /* _ASMARM64_GIC_V3_ITS_H_ */
@@ -97,3 +97,16 @@ void its_init(void)
its_cmd_queue_init();
}
+/* must be called after gicv3_enable_defaults */
+void its_enable_defaults(void)
+{
+ int i;
+
+ /* Allocate LPI config and pending tables */
+ gicv3_lpi_alloc_tables();
+
+ for (i = 0; i < nr_cpus; i++)
+ gicv3_lpi_rdist_enable(i);
+
+ writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
+}
its_enable_defaults() enable LPIs at distributor level and ITS level. gicv3_enable_defaults must be called before. Signed-off-by: Eric Auger <eric.auger@redhat.com> --- v4 -> v5: - some reformattings moved to earlier patch - add assert(!gicv3_redist_base()) in alloc_lpi_tables() - revert the usage of for_each_present_cpu() v3 -> v4: - use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_baser() - don't parse BASERs again in its_enable_defaults - rename its_setup_baser into its_baser_alloc_table - All allocations moved to the init function - squashed "arm/arm64: gicv3: Enable/Disable LPIs at re-distributor level" into this patch - introduce gicv3_lpi_rdist_enable and gicv3_lpi_rdist_disable - pend and prop table bases stored as virt addresses - move some init functions from enable() to its_init - removed GICR_PROPBASER_IDBITS_MASK - introduced LPI_OFFSET - lpi_prop becomes u8 * - gicv3_lpi_set_config/get_config became macro - renamed gicv3_lpi_set_pending_table_bit into gicv3_lpi_set_clr_pending v2 -> v3: - introduce its_setup_baser in this patch - squash "arm/arm64: ITS: Init the command queue" in this patch. --- lib/arm/asm/gic-v3.h | 13 +++++++++++++ lib/arm/gic-v3.c | 25 +++++++++++++++++++++++++ lib/arm64/asm/gic-v3-its.h | 1 + lib/arm64/gic-v3-its.c | 13 +++++++++++++ 4 files changed, 52 insertions(+)